1t1c

# 1T1C: The One-Transistor-One-Capacitor DRAM Cell — Charge Storage Physics, Array Sensing, and the Capacitor Scaling Moat

The 1T1C cell — one access transistor plus one storage capacitor — is the physical unit that every byte of DRAM is built from. The transistor is nothing more than a switch: when its word line is on, it connects a tiny capacitor to a bit line; when it is off, the capacitor is isolated and whatever charge sits on it — present or absent — is the "1" or the "0." It is the simplest possible way to store a bit in silicon, and for over fifty years it has stayed simpler, cheaper, and denser than every rival memory architecture that has tried to displace it.

Writing a bit is just charging or draining the capacitor. Raise the word line, the access transistor turns on, and the bit line's voltage — driven to either a logic-high or logic-low rail by the write driver — flows straight onto the storage node until the capacitor sits at that same voltage. Drop the word line and the transistor opens the switch again, trapping that charge behind it. The entire write operation is governed by one relationship:

where $C_s$ is the storage capacitance and $V_{cell}$ is the voltage the capacitor was charged to. Every downstream problem in DRAM design — how to read the bit back out, how long the bit survives, how small the cell can be made — is a consequence of how small $Q$ is allowed to get before it stops being usefully measurable.

That sharing step is the entire reason DRAM sensing is hard. The bit line is precharged to the midpoint voltage $V_{dd}/2$ before the word line ever turns on. The moment it does, the storage capacitor's charge redistributes across the combined capacitance of the cell and the much larger bit line, by simple charge conservation:

With a typical storage capacitance around 25 femtofarads and a bit-line parasitic capacitance roughly ten times larger, $\Delta V$ comes out to only tens of millivolts. A differential sense amplifier compares that shifted bit line against a reference line held at exactly $V_{dd}/2$ and latches the difference to a full logic level — which is also why every DRAM read is destructive: the act of sensing drains the cell, and the row must be written back immediately after every access.

The retention problem is the mirror image of the write problem. Once the access transistor turns off, the storage node is never perfectly isolated — subthreshold leakage through the "off" transistor and junction leakage at the storage diffusion both bleed charge away continuously. The decay is a simple RC discharge:

and because leakage current through silicon junctions is thermally activated — roughly doubling for every 8–11°C rise, the same Arrhenius behavior that governs reaction rates throughout semiconductor processing — a cell that comfortably holds its charge for 64 milliseconds at room temperature can fail in a fraction of that time in a hot server rack. That is why every DRAM standard specifies a maximum refresh interval (typically 32 or 64 ms depending on density and temperature grade) and why JEDEC doubles the refresh rate above 85°C: the controller is racing the exponential, not a fixed clock.

Refresh is not free — it is a recurring tax on bandwidth and power. Every row in a DRAM array must be read and rewritten before its refresh window expires, which means a controller is constantly stealing cycles away from the workload to keep every one of billions of cells alive. As cell counts per die have grown node over node, the number of rows that fit inside the same refresh window has grown with them, so the fraction of total DRAM time and energy spent purely on refresh — rather than useful reads and writes — has climbed for every generation of density scaling. Shrinking $C_s$ even a little makes this worse twice over: a smaller cell holds less charge to begin with, *and* a given leakage current drains a smaller reservoir faster, which is why DRAM makers have fought so hard to hold $C_s$ roughly constant across nodes even as the cell's physical footprint has shrunk by orders of magnitude.

That constancy is the actual toll bridge. Holding capacitance steady while the footprint shrinks means the only lever left is height: capacitor aspect ratios have climbed from roughly 10:1 in the 1990s to 70–90:1 today, which means etching and then conformally depositing a high-k dielectric into holes that are over eighty times taller than they are wide, without a single void or thickness variation anywhere along that depth. Only three companies — Samsung, SK hynix, and Micron — currently run this process at competitive yield and volume; each new node requires billions of dollars of new deep-etch and atomic-layer-deposition capacity that is useless for anything but this exact geometry. A fabless company cannot simply license a DRAM design the way it licenses a logic core, because the entire value is locked inside a capacitor-fabrication process that took decades of proprietary process learning to get to 80:1 without a yield collapse — which is why DRAM, unlike logic, has never had a serious "pure-play foundry" business model: the capacitor moat and the memory-maker are the same company.

Read 1T1C through a *charge-conservation* lens rather than a *transistor-count* lens: the number that actually decides whether a DRAM generation works is how much charge survives from $Q = C_s V_{cell}$ at write time through to $\Delta V = V_{cell} \cdot C_s/(C_s+C_{BL})$ at read time, after an exponential leak $V(t) = V_0 e^{-t/\tau}$ has been eating away at it the entire time in between. Every hard problem in DRAM scaling — taller capacitors, higher-k dielectrics, faster refresh at temperature, ever more sensitive sense amps — is a different way of keeping that one surviving charge large enough to measure.