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Build the future of AI silicon.

The AI-chip development platform for engineers and researchers — design, process, simulate, and manufacture next-generation AI, ML, and Transformer chips. Ask anything below to start building.

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Every simulation runs on our integrated compute fabric — two AWS cloud servers plus seven dedicated compute machines working together — so you get fast, professional results in your browser. No install, no setup.

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For engineers & researchers building AI silicon

From concept to fab — develop AI chips end-to-end

ChipFoundryServices is an AI-chip development platform for semiconductor and AI professionals. Design architectures, model process modules, run simulations, plan manufacturing, and build machine-intelligence knowledge — with an AI copilot (CFSGPT) trained across chip design, fab process, and modern AI. Covering the full stack: Artificial Intelligence, Machine Learning, Deep Learning, Large Language Models, AI agents, and AI Transformer chip architecture.

Built for teams at
Three paths · one for every role in the AI chip stack
Design & Architecture

Silicon Architect Track

For design, architecture & verification engineers at Nvidia, AMD, Apple & Intel.

  • AI chip & accelerator architecture
  • Transformer & neural-network hardware
  • RTL, verification & design flow
  • Simulation & performance modeling
Process & Manufacturing

Fab & Process Track

For process, equipment & yield engineers at TSMC, ASML, Applied Materials, Lam & KLA.

  • Process modules: Etch, CVD, PVD, CMP, Litho
  • Metrology, defect & yield with ML
  • Equipment, hardware & RF design
  • Manufacturing productivity & MES
AI & Systems

AI Systems Track

For AI, ML & infra engineers at Anthropic, OpenAI, Microsoft, Amazon & Oracle.

  • LLMs, deep learning & agents
  • Training & inference on AI silicon
  • Co-design of models & hardware
  • Physics & ML-driven simulation
AI Chip Development Hub · what you can build here
🧩
AI Chip Design

RTL to layout, accelerator microarchitecture, and design-flow guidance for AI silicon.

🏗️
AI Chip Architecture

Dataflow, memory hierarchy, and systolic/neuromorphic architectures for ML workloads.

🔀
AI Transformer Chip

Attention-optimized hardware, tensor engines, and transformer accelerator design.

🔬
AI Chip Process

Etch, deposition, litho, CMP and process integration for advanced nodes.

🏭
AI Chip Manufacturing

Fab flow, yield, metrology, and defect reduction powered by machine learning.

📈
AI Chip Productivity

Throughput, OEE, preventive maintenance, and MES optimization with AI.

🧮
AI Chip Simulation

Device, circuit, thermal, and physics-based simulation plus synthetic data.

🔬
Plasma Etch Simulator · Live

Run an RIE/ICP trench-profile simulation on the compute pool — depth, undercut, sidewall angle.
🧪
Deposition / Step-Coverage · Live

Run a CVD/ALD conformal-fill simulation — step coverage, conformality, keyhole voids.
🧠
Transformer Inference · Live

Model LLM serving on an AI accelerator — throughput, latency, KV-cache, roofline bottleneck.
🔬
Lithography Aerial Image · Live

Image a line/space grating through the lens — CD, contrast/NILS, k1, depth of focus, EUV vs 193i.
🪞
CMP Planarization · Live

Chemical-mechanical polishing — Preston removal rate, planarization time constant, step-height clearing, dishing and erosion, and a planarity verdict.
🔌
Interconnect RC & EM · Live

Copper BEOL wiring — size-effect resistivity rise, distributed-line RC signal delay, and Black’s-equation electromigration lifetime, with a wire-health verdict.
🌡️
Thermal & Hotspot · Live

Junction-temperature stack — temperature-dependent silicon conductivity, hotspot spreading, and the thermal margin against Tⱼ,max with a throttling verdict.
⚡
Transistor I-V · Live

GAA/FinFET electrostatics — the screening length that sets gate control, subthreshold swing & DIBL, and a velocity-saturated I-V with an Iₒₙ/Iₒ꜀ switch-quality verdict.
💠
Die Yield & Cost · Live

Wafer economics — gross-die-per-wafer packing inside the edge-exclusion ring, four defect-limited yield models (Poisson, Murphy, negative-binomial, Seeds), and the cost-per-good-die that prices a GPU.
🧠
6T SRAM Stability · Live

Bit-cell margins — the butterfly-curve hold & read Static Noise Margin, the cell-ratio read-stability vs pull-up-ratio writeability trade, and the statistical Vth-mismatch Vmin that floors a cache array.
🧮
Systolic Array · Live

AI-accelerator dataflow — map a Transformer GEMM onto an R×C PE grid for the roofline & ridge point, spatial×temporal PE utilization, the HBM-vs-compute bottleneck, on-chip SRAM tile fit, latency and TOPS/W.
📶
HBM Bandwidth · Live

High-Bandwidth Memory roofline — peak vs effective bandwidth from DRAM efficiency (row-buffer hits, read/write turnaround, refresh), page-hit & random latency, and the memory-bound LLM decode token rate that HBM bandwidth gates.
🗃️
KV Cache · Live

Transformer attention-memory model — per-token Key/Value cache cost from layers, KV heads & head dim, total HBM footprint (weights + cache), capacity fit / OOM, max batch & context, and the memory-bound decode throughput long-context serving gates.
🏋️
Training Memory · Live

LLM training-step memory model — mixed-precision Adam model states (weights + gradients + optimizer = 16 bytes/param) plus activations, how ZeRO/FSDP sharding and activation checkpointing shrink per-GPU HBM, whether a step fits, and the minimum GPU count a run needs.
⚡
Power & Thermal · Live

Chip power & thermal-budget model — dynamic switching power (activity × C × V² × f) plus interconnect and thermally-coupled leakage, a junction-temperature fixed-point solve, TDP/Tjmax fit, thermal-runaway detection, and the thermal-limited maximum clock the cooling can sustain.
🔀
3D Parallelism · Live

Distributed-training model — split an LLM step across a GPU cluster (num_gpus = TP × PP × DP), roofline the per-GPU compute, then add the tensor-parallel activation all-reduces, pipeline point-to-point + fill/drain bubble, and backward-overlapped data-parallel gradient all-reduce to get step time, MFU, bottleneck, and throughput.
🛡️
Reliability & Aging · Live

Device wear-out model — age a transistor along BTI (Vth creep ∝ t^0.16), HCI (damage ∝ √switching-cycles, Vds⁴) and TDDB (oxide MTTF ∝ Eox⁻⁴⁰). Accumulate the threshold-voltage shift against the timing guardband, then combine wear-out and oxide breakdown as competing risks to get the MTTF, dominant mechanism and frequency degradation.
🧩
Place & Route · Live

EDA physical-design model — estimate the average net length from Rent's rule (∝ N^(p−0.5)), balance routing demand against the metal-stack track supply for a congestion number, then walk a logic+interconnect critical path with a congestion detour penalty to get Fmax and timing slack, sweeping placement utilization to find the density/congestion/timing sweet spot.
🔌
Power Delivery · Live

Power-integrity model — static IR-drop (I·R) plus the L·di/dt transient droop as the package inductance rings against the on-die decap, with the anti-resonance peak impedance Z_peak = L/(R·C) and resonant frequency, judged against the voltage-margin budget and the target-impedance criterion, sweeping decap to find the droop knee and the PDN-resistance sweet spot.
🔢
Quantization · Live

LLM low-precision model — take weights, activations and the KV-cache from FP16 down to INT8/INT4/FP8, with per-group scale overhead (effective bits = bits + 16/group_size), the memory footprint and bandwidth-bound decode speed-up, and a uniform-quantization SQNR accuracy proxy that maps the worst of the three error sources to a quality-retention percentage, verdict and dominant error source.
⚡
FlashAttention · Live

Attention-kernel roofline model — contrast naive attention (materializes the S×S score matrix in HBM, quadratic bytes) against FlashAttention (tiles Q/K/V into SRAM with online softmax, linear bytes). Compute the HBM-traffic reduction, arithmetic intensity and the roofline flip from memory-bound to compute-bound, the SRAM tile fit, causal-mask savings, wall-clock speed-up and achieved TFLOP/s.
🔀
Mixture-of-Experts · Live

Sparse MoE routing model — a gating network sends each token to its top-k of N experts, so only k/N of the parameters are active and the layer does ~N/(capacity·k) less matmul than a dense FFN of the same size. Compute the routing sparsity, per-expert load distribution, tokens dropped above capacity and compute wasted on padding below it, the capacity U-curve, and the expert-parallel all-to-all traffic that turns MoE communication-bound at scale.
⏳
Electromigration · Live

Interconnect wire-lifetime model — current density J=I/(w·t) drives electromigration, and Black's law MTTF=A·J⁻ⁿ·exp(Ea/kT) sets how long a metal line survives. Compute the current density, mean-time-to-failure and FIT rate, the Blech immortality threshold (jL product), the maximum current density budget Jmax(T) for a target lifetime, headroom against that budget, and the temperature acceleration behind interconnect reliability sign-off.
🕐
Clock Tree Skew & Jitter · Live

Clock distribution timing model — random skew accumulates through the buffer tree as σ√(2·depth), systematic skew comes from wire-RC mismatch across the die, and jitter adds random (supply-noise) plus duty-cycle distortion. Compute insertion delay, total skew, peak-to-peak jitter, the combined clock uncertainty as a percent of the period, the timing-uncertainty budget and headroom, the maximum clock frequency fmax, and clock-tree power — the timing closure behind every synchronous chip.
🕸️
Network-on-Chip Latency & Throughput · Live

On-chip interconnect fabric model — a mesh or torus of routers carries packets between cores, and average hop count, router-pipeline delay and serialization set the zero-load latency while queueing theory sets how it blows up near saturation. Compute average hops, zero-load and loaded latency, the saturation injection rate (η·c/k), link and bisection bandwidth, aggregate accepted throughput, and latency headroom against budget — the communication backbone behind every many-core and AI-accelerator die.
🌡️
2.5D / CoWoS Package Thermal & Warpage · Live

Advanced-package sign-off model — junction heat escapes through the die-to-lid TIM, copper lid, lid-to-heatsink TIM and heatsink in series, setting θ_JA and Tj = T_ambient + P·θ_JA against Tj_max; meanwhile the silicon interposer bonded to an organic substrate bends like a bimetal on cooling from the mold-cure temperature, giving Timoshenko CTE-mismatch warpage. Compute the θ_JA resistance stack and its dominant layer, junction temperature and headroom, raw and net coplanarity warpage after the stiffener knock-down, and whether the package clears both the thermal and JEDEC coplanarity gates — the physical-integration wall behind every chiplet accelerator.
💡
Silicon Photonics / Co-Packaged Optics · Live

Optical link-budget model — as AI clusters outgrow copper SerDes, the interconnect moves onto the package as silicon photonics: an integrated laser feeds a ring/Mach–Zehnder modulator, light couples off the die into fibre and lands on a Ge photodetector + TIA. Sum the optical loss stack (modulator + two couplers + waveguide + fibre + WDM), derive the received power, compute the TIA-noise-limited receiver sensitivity for the target BER with the PAM4 penalty, and get the link margin, the WDM aggregate Tb/s and the energy-per-bit — a link ships only if it closes the budget and beats the pJ/bit target. The optical-I/O trade behind co-packaged optics for next-generation AI fabrics.
❄️
Datacenter Chip Cooling Loop · Live

Thermal-loop model for AI accelerators — as training silicon pushes past 700 W–1 kW, the heat path becomes a resistance network from the junction, through two thermal-interface layers and a copper lid, into a liquid cold plate (or a two-phase/immersion evaporator), and out to the facility coolant. Sum the series conduction resistances (TIM1, lid, TIM2, plate base), the convective film resistance, and the caloric resistance (the coolant self-heats as it carries the load) into θ_JA; Tj = coolant_inlet + Q·θ_JA must stay under Tj_max. Moving coolant costs pump/fan power (ΔP grows ~flow¹·⁷⁵), so buying margin with flow burns parasitic watts. Compare cold-plate, two-phase and air, and see whether the design clears both the thermal and cooling-overhead gates — the liquid-cooling wall behind every high-power AI package.
⚡
Speculative Decoding · Live

Draft/target throughput model — a small draft model guesses the next γ tokens and the big target verifies all of them in one memory-bound pass. Compute the expected tokens accepted per step E=(1−α^(γ+1))/(1−α), the draft/verify latency split, the net speedup over plain autoregressive decoding, the optimal speculation length, and the regime (draft-limited, verify-compute-bound or low-acceptance) behind vLLM, Medusa and EAGLE serving.
🧩
Chiplet & Advanced Packaging · Live

Disaggregation economics model — defect-limited yield is super-linear in die area, so N small chiplets each yield far better than one reticle-sized SoC. Compare monolithic vs chiplet cost per good part, known-good-die escapes and per-join assembly yield, the die-to-die beachfront bandwidth and pJ/bit energy of organic MCM, EMIB, CoWoS interposer and 3D hybrid bond, and the optimal chiplet count behind AMD MI300, Intel Foundry EMIB/Foveros and TSMC CoWoS/SoIC.
🔗
SerDes & Die-to-Die Link Budget · Live

Signal-integrity link-budget model — a lane at rate R with b bits/symbol runs at baud R/b and Nyquist baud/2, so PAM4 halves the Nyquist of NRZ but each of three sub-eyes is a third of the swing. Channel insertion loss (skin + dielectric) shrinks the received eye; noise is the RSS of crosstalk, residual ISI and a thermal floor; Q sets raw BER and RS-FEC (KP4) buys coding gain to 1e-15. Compare NRZ vs PAM4 over interposer / organic / long-reach PCB, link margin in dB, pJ/bit and lane power, the beachfront lane fit at a bump pitch, and the fastest rate a channel closes — the UCIe/BoW, 112G/224G PAM4 and OIF-CEI trade behind Intel, TSMC, AMD, Nvidia, Marvell and Broadcom.
🗂️
Cache Hierarchy & Average Memory Access Time · Live

Memory-hierarchy model — a working set spans W/line cache lines and each level earns a cumulative hit rate H(cov)=cov^(1-locality) as capacity and locality rise. The telescoping Average Memory Access Time = t_L1 + (1-H1)·t_L2 + (1-H2)·t_L3 + (1-H3)·t_mem charges each level only for the accesses that miss above it; LLC MPKI sets the miss stream and MLP-aware stall CPI = API·(Average Memory Access Time-L1)/MLP hides latency. Size L1/L2/L3, line, clock, locality, memory latency, HBM/DDR bandwidth, MLP and cores to see the per-level hit rates, Average Memory Access Time in ns and cycles, MPKI, slowdown and whether the workload is latency-, bandwidth-, capacity-bound or cache-resident — the memory-wall trade behind AI inference, training and HPC at Intel, TSMC, AMD, Nvidia, Apple and Anthropic.
📚
Knowledge Build-up

An AI copilot over 13k+ curated entries spanning chips, process, and AI.

📘
English Lesson 1

Practice greetings, names, audio pronunciation, and a short quiz before college.
Full curriculum · the complete AI & semiconductor stack
🧠 AI, ML & Agents
Artificial Intelligence Machine Learning Deep Learning Large Language Models AI Agents Transformer Architecture Neural Networks Machine Intelligence Mathematics Science Statistics Science
🔧 Chip Design, Architecture & Mfg
Chip Design AI Chip Design AI Chip Architecture AI Transformer Chip AI Chip Simulation AI Chip Manufacturing AI Chip Processing AI Chip Productivity Fabrication Manufacturing
⚙️ Equipment Engineering
Equipment Development Hardware Component Mechanical Design Electrical Design Software Design Simulation Design Radio Frequency Cable Design
🔬 Process Modules
Plasma Etch Wet Etch CVD PVD CMP Metrology Litho Implant Diffusion Clean Tech
🏭 Fab Facilities & Infrastructure
Clean Room Facility Heat Exchanger Chiller AC Rack Network MES Green to Green
🧪 Test, Support & Reliability
Function Test Process Test Productivity Test Hardware Test Test Workbench Tool Box Preventive Maintenance Corrective Maintenance Defect Troubleshooting Technical Product Support Global Product Support Product Improvement
🔭 Applied Sciences & Safety
Physics Chemistry Chemical Reaction Material Science & Engineering Process Engineering Engineering Safety
Live applications · demos, raw data & reports
Applications · every tool we have built, live on the compute pool

Everything below is running now on ChipFoundryServices — interactive demos for the semiconductor and AI / ML / DL / LLM / Agent and auto-programming community. Each application is a real, reduced-order engineering model served from our distributed compute pool, with a matching raw-JSON endpoint you can call from any tool and a machine-readable report for every run.

● LIVE
📚
CFSGPT Knowledge Copilot

An AI copilot over 13,000+ curated entries across chip design, process, architecture, and AI. Flagship answers with styled tables, hand-drawn diagrams, and rendered math.

JSON · /api.php?q= ● LIVE
🔬
Plasma Etch Simulator

Reduced-order RIE / ICP trench-profile model — depth, undercut, CD top and bottom, sidewall angle, aspect ratio, and anisotropy, with a full etched-wall profile.

JSON · /edge/simulate ● LIVE
🧪
CVD / ALD Deposition

Conformal step-coverage model — top, sidewall, and bottom thickness, conformality, remaining opening, pinch-off detection, and a plain-language fill-quality verdict.

JSON · /edge/deposit ● LIVE
🧠
Transformer-Chip Inference

LLM-serving roofline — decode tokens/s, time-to-first-token, end-to-end latency, KV-cache size, HBM fit, compute-vs-memory bottleneck, and the efficient batch size.

JSON · /edge/infer ● LIVE
🔭
Lithography Aerial Image

Abbe partial-coherence imaging — printed line and space CD, image contrast and NILS, k1 factor, Rayleigh half-pitch, depth of focus, and a resolvability verdict.

JSON · /edge/litho ● LIVE
🪞
CMP Planarization

Chemical-mechanical polishing — Preston-law blanket removal rate, planarization time constant, step-height clearing, post-polish dishing and erosion, and a planarity verdict.

JSON · /edge/cmp ● LIVE
🔌
Interconnect RC & EM

Copper BEOL wiring — Fuchs–Sondheimer size-effect resistivity, distributed-line RC signal delay, and Black’s-equation electromigration lifetime, with a wire-health verdict.

JSON · /edge/interconnect ● LIVE
🌡️
Thermal & Hotspot

Chip junction temperature — self-consistent junction-to-ambient resistance stack, temperature-dependent silicon conductivity, and hotspot spreading, with a Tⱼ,max throttling verdict.

JSON · /edge/thermal ● LIVE
⚡
GAA/FinFET Transistor

The switch under every AI accelerator — electrostatic screening length, subthreshold swing and DIBL, threshold roll-off, and velocity-saturated I-V curves, with an Iₒₙ/Iₒ꜀ switch-quality verdict.

JSON · /edge/transistor ● LIVE
💠
Die Yield & Cost

What a wafer actually produces — gross-die-per-wafer packing inside the edge-exclusion ring, the Poisson / Murphy / negative-binomial / Seeds defect-yield models, and the cost-per-good-die that sets the price of an accelerator die.

JSON · /edge/yield ● LIVE
🧠
6T SRAM Stability

Whether a bit holds — the butterfly-curve hold & read Static Noise Margin, the cell-ratio (read) vs pull-up-ratio (write) tug-of-war, and the statistical Vth-mismatch Vmin that sets the floor voltage of an accelerator's on-die cache.

JSON · /edge/sram ● LIVE
🧮
Systolic Array / AI Accelerator

Whether the array actually works — map a Transformer GEMM onto an R×C PE grid for the roofline & ridge point, spatial×temporal PE utilization, the HBM-bandwidth-vs-compute bottleneck, on-chip SRAM tile fit, and latency and TOPS/W.

JSON · /edge/systolic ● LIVE
📶
HBM Memory Bandwidth

Why inference is memory-bound — model HBM3/HBM3E stacks for peak vs effective bandwidth after DRAM efficiency (row-buffer hits, read/write turnaround, refresh), page-hit & random latency, and the LLM decode token rate bandwidth gates.

JSON · /edge/hbm ● LIVE
🗃️
KV Cache / Attention Memory

Why long-context serving is a memory problem — per-token Key/Value cache cost from layers, KV heads & head dim, total HBM footprint (weights + cache), capacity fit / OOM, max batch & context, grouped-query & KV-quant savings, and the decode throughput footprint gates.

JSON · /edge/kvcache ● LIVE
🏋️
LLM Training Memory

Why training is far hungrier than inference — mixed-precision Adam model states (weights + gradients + fp32 master + moments = 16 bytes/param) plus activation memory, how ZeRO/FSDP stages 1–3 shard across GPUs, how activation checkpointing makes long sequences fit, per-GPU HBM fit, and the minimum GPU count a run needs.

JSON · /edge/training ● LIVE
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Power & Thermal Budget

Where a processor's watts go — dynamic switching power (activity × C × V² × f), interconnect/wire power, and thermally-coupled leakage that doubles roughly every 15 °C. Solve the junction-temperature fixed point, check TDP and Tjmax, detect thermal runaway, and find the thermal-limited maximum clock — the trade-offs that set an AI accelerator's power envelope.

JSON · /edge/power ● LIVE
🔀
3D Parallelism & All-Reduce

How an LLM training step splits across a GPU cluster — num_gpus = TP × PP × DP. Roofline the per-GPU compute, then layer the tensor-parallel activation all-reduces, the pipeline point-to-point sends and fill/drain bubble, and the backward-overlapped data-parallel gradient all-reduce. Get step time, strong-scaling efficiency / MFU, the dominant bottleneck, and token throughput.

JSON · /edge/parallelism ● LIVE
🛡️
Device Reliability & Aging

How a transistor wears out under bias and temperature — BTI threshold-voltage creep (∝ t^0.16), hot-carrier injection that grows with switching cycles (Vds⁴), and time-dependent dielectric breakdown (MTTF ∝ Eox⁻⁴⁰). Accumulate the Vth shift against the timing guardband, get the wear-out life, competing-risk MTTF, dominant mechanism, and frequency degradation across the datacenter, mobile, and automotive corners.

JSON · /edge/reliability ● LIVE
🧩
EDA Place & Route

Whether a block routes clean and closes timing. Estimate the average net length from Rent's rule (∝ N^(p−0.5) with the standard-cell pitch), balance routing demand against the track supply the metal stack provides for a congestion number, then walk a logic + interconnect critical path — with a congestion-driven detour penalty — for Fmax and timing slack. Sweep placement utilization to expose the density/congestion/timing sweet spot at the datacenter, GPU-block, and congested corners.

JSON · /edge/placeroute ● LIVE
🔌
Power-Delivery Network

Whether a power rail stays inside its voltage margin. Compute the static IR-drop (I·R) plus the L·di/dt transient droop as the package inductance rings against the on-die decap, the anti-resonance peak impedance Z_peak = L/(R·C) and resonant frequency, and judge total droop against the voltage-margin budget and the target-impedance criterion Z_target = ΔV/ΔI. Sweep decap to find the droop knee, and the PDN-resistance sweet spot where too little R rings and too much piles on IR-drop.

JSON · /edge/pdn ● LIVE
🔢
LLM Quantization

How far you can drop precision before quality breaks. Take weights, activations and the KV-cache from FP16 to INT8/INT4/FP8, with per-group scale overhead (effective bits = bits + 16/group_size), the memory footprint and bandwidth-bound decode speed-up, and a uniform-quantization SQNR accuracy proxy (SQNR ≈ 6.02·bits + 1.76 − 20·log₁₀ crest) that maps the worst of the three error sources to a quality-retention percentage. Contrast per-channel vs per-tensor grouping and W4A16 vs W4A4 to see the accuracy/compression knee.

JSON · /edge/quantization ● LIVE
⚡
FlashAttention Kernel

Why attention got fast without changing the math. Naive attention writes the S×S score matrix to HBM — memory traffic quadratic in context — while FlashAttention tiles Q/K/V into SRAM and streams an online softmax, never materializing the matrix, so HBM traffic is linear in S. See the roofline flip: cutting bytes lifts arithmetic intensity (FLOP/byte) past machine balance, moving attention from memory-bound to compute-bound at the same FLOPs. Tune SRAM budget, block size, causal masking and precision to watch the tile fit and the speed-up.

JSON · /edge/flashattention ● LIVE
🔀
Mixture-of-Experts Routing

How frontier LLMs scale parameters without scaling compute. A gating network routes each token to only its top-k of N experts, so just k/N of the weights are active and the layer does ~N/(capacity·k) less matmul than a dense FFN of the same total size. But experts run as fixed-size batches: tokens above capacity are dropped, cold experts pad slots with dead compute — the capacity U-curve. Tune experts, top-k, capacity factor, load imbalance and expert parallelism to see the drop-vs-waste trade and the all-to-all traffic that turns MoE communication-bound.

JSON · /edge/moe ● LIVE
⏳
Electromigration & Wire Lifetime

Why interconnect metal wears out and how long it lasts. Current density J=I/(w·t) drives electromigration; Black's law MTTF=A·J⁻ⁿ·exp(Ea/kT) sets the mean-time-to-failure of a copper line. Below the Blech jL threshold the wire is immortal — backstress cancels the flux. Compute current density, MTTF and FIT rate, the Blech immortality product, the Jmax(T) current-density budget for a target lifetime, headroom against it and the temperature acceleration behind interconnect reliability sign-off.

JSON · /edge/electromigration ● LIVE
🕐
Clock Tree Skew & Jitter

Whether every flip-flop on the die sees the clock edge at the same instant. Random skew accumulates through the buffer tree as σ√(2·depth); systematic skew comes from wire-RC mismatch across the floorplan; jitter adds random supply-noise plus duty-cycle distortion. Total clock uncertainty (skew + jitter) eats into the cycle — compute insertion delay, skew, peak-to-peak jitter, uncertainty as a percent of period, the budget and headroom, fmax, and clock-tree power. An H-tree balances delay; a clock mesh trades power to crush systematic skew.

JSON · /edge/clocktree ● LIVE
🕸️
Network-on-Chip Latency & Throughput

How packets move between cores on a many-core die. A mesh or torus of routers carries flits hop by hop; average hop count, router-pipeline stages and serialization set the zero-load latency, and queueing theory sets how latency explodes as offered load nears the saturation injection rate η·c/k. Compute average hops, zero-load and loaded latency, saturation throughput, link and bisection bandwidth, aggregate accepted throughput, and latency headroom against budget. A torus halves the hops and doubles the bisection of a mesh at the cost of wrap-around wiring.

JSON · /edge/noc ● LIVE
🌡️
2.5D / CoWoS Package Thermal & Warpage

Whether a high-power chiplet package survives sign-off. Junction heat escapes through a series thermal stack — die-to-lid TIM, copper lid, lid-to-heatsink TIM and heatsink — that adds to θ_JA, so Tj = T_ambient + P·θ_JA must stay under Tj_max. Meanwhile the silicon interposer bonded to an organic substrate bends like a bimetallic strip on cooling from the mold-cure temperature, and Timoshenko curvature times the package span squared gives the coplanarity warpage that stiffeners knock down. Compute the θ_JA stack and its dominant resistor, junction temperature and headroom, raw and net warpage, and whether it clears both the thermal and JEDEC coplanarity gates.

JSON · /edge/warpage ● LIVE
💡
Silicon Photonics & Co-Packaged Optics

Whether a co-packaged optical link closes. As AI clusters outgrow copper SerDes, the interconnect moves onto the package: an integrated laser feeds a ring/Mach–Zehnder modulator, light couples off the die through a grating coupler into fibre and lands on a Ge photodetector + TIA. Launch power minus the modulator, two couplers, waveguide, fibre and WDM losses gives the received power, which must clear the TIA-noise-limited receiver sensitivity (worse at higher rate and under PAM4). Tune the loss stack, data rate, responsivity, WDM channels and laser efficiency to see the link margin in dB, the aggregate Tb/s and the pJ/bit — and whether the link closes and beats its energy budget.

JSON · /edge/photonics ● LIVE
❄️
Datacenter Chip Cooling Loop

Whether an AI accelerator stays cool — and worth cooling. As training silicon pushes past 700 W–1 kW, the heat path becomes a resistance network from the junction, through two thermal-interface layers and a copper lid, into a liquid cold plate (or a two-phase/immersion evaporator), and out to the facility coolant. The series conduction resistances, the convective film resistance and the caloric coolant self-heating sum to θ_JA, so Tj = coolant_inlet + Q·θ_JA must stay under Tj_max. Moving coolant costs pump/fan power (ΔP grows ~flow¹·⁷⁵), so buying thermal margin with flow burns parasitic watts. Compare cold-plate, two-phase and air, tune the thermal stack and flow, and see the θ_JA resistance breakdown, junction temperature and headroom, the cooling overhead as a percent of TDP, and whether the design clears both the thermal and overhead gates.

JSON · /edge/cooling ● LIVE
⚡
Speculative Decoding

How LLM serving decodes several tokens per step. Autoregressive decode is memory-bound — one full weight read per token — so a small draft model proposes γ tokens and the big target verifies all γ+1 in a single still-memory-bound pass, accepting E=(1−α^(γ+1))/(1−α) of them. Tune the draft/target sizes, acceptance rate α, speculation length γ and hardware to see the net speedup, the draft-vs-verify latency split, the optimal γ, and whether you're draft-limited, verify-compute-bound or acceptance-limited — the throughput trade behind vLLM, Medusa and EAGLE.

JSON · /edge/specdec ● LIVE
🧩
Chiplet & Advanced Packaging

When splitting a giant monolithic accelerator into chiplets pays off. Defect-limited yield is super-linear in die area — one reticle-sized SoC can yield below 50% — so N smaller chiplets each yield far better, but you pay for a package, lose parts at assembly and burn energy across die boundaries. Tune the design area, chiplet count, defect density, packaging class, known-good-die coverage and die-to-die traffic to see the cost per good part, system yield, beachfront bandwidth and optimal N — the packaging trade behind AMD MI300, Intel Foveros and TSMC CoWoS.

JSON · /edge/chiplet ● LIVE
🔗
SerDes & Die-to-Die Link Budget

Whether a high-speed lane closes. A lane at rate R with b bits/symbol runs at baud R/b and Nyquist baud/2 — PAM4 halves NRZ's Nyquist but each sub-eye is a third of the swing. Channel insertion loss shrinks the received eye; crosstalk, residual ISI and a thermal floor set the noise; Q gives the raw BER and RS-FEC (KP4) buys coding gain to 1e-15. Tune rate, modulation, channel, reach, lanes, pitch and FEC to see the link margin in dB, pJ/bit and lane power, the beachfront lane fit and the fastest rate that closes — the signal-integrity trade behind UCIe/BoW and 112G/224G PAM4.

JSON · /edge/serdes ● LIVE
🗂️
Cache Hierarchy & Average Memory Access Time

What actually bounds a workload's memory. A working set spans W/line cache lines and each level earns a cumulative hit rate H(cov)=cov^(1-locality) as capacity and locality rise. The telescoping Average Memory Access Time = t_L1 + (1-H1)·t_L2 + (1-H2)·t_L3 + (1-H3)·t_mem charges each level only for misses above it; LLC MPKI sets the miss stream and MLP-aware stall CPI hides latency. Size L1/L2/L3, line, clock, locality, memory latency, HBM/DDR bandwidth, MLP and cores to see the per-level hit rates, Average Memory Access Time in ns and cycles, MPKI, slowdown and whether you're latency-, bandwidth-, capacity-bound or cache-resident.

JSON · /edge/cache ● LIVE
🛰️
CFS Edge Compute Pool

A seven-node distributed compute fabric with automatic failover. Every simulation above runs here; the dashboard reports live per-node test results across the pool.

Dashboard · /edge/ ● LIVE
📱
CFS Super App

An installable progressive web app for chip and AI engineers — chat and collaboration that runs full-screen from your phone's Home Screen.

PWA · /app/ ● LIVE
📘
English Lesson 1

An interactive English-learning module — greetings and names, tap-to-play audio pronunciation, vocabulary flashcards, a dialogue, and an auto-graded quiz.

Web + App · /english/
Raw JSON data access · call any application from your own tools
ApplicationMethod & endpointExample requestReturns (JSON)
CFSGPT Knowledge GET /api.php?q={query} /api.php?q=what+is+euv { response } — a full Markdown answer (prose, tables, diagrams, math).
Plasma Etch GET /edge/simulate?{params} /edge/simulate?etch_time_s=120&source_power_w=800 model, inputs, outputs (depth_nm, cd_top_nm, sidewall_angle_deg, aspect_ratio, anisotropy), profile wall polyline.
Deposition GET /edge/deposit?{params} /edge/deposit?trench_width_nm=100&sticking_coeff=0.1 outputs (step_coverage_pct, conformality_pct, pinch_off, fill_quality), profile fill polyline.
Inference GET /edge/infer?{params} /edge/infer?params_b=70&batch=64 outputs (decode_tokens_s, ttft_ms, kv_cache_gb, fits_in_hbm, efficient_batch), profile.batch_curve.
Lithography GET /edge/litho?{params} /edge/litho?wavelength_nm=13.5&na=0.55 outputs (printed_line_cd_nm, nils, k1_factor, depth_of_focus_nm, resolvable), profile.aerial intensity curve.
CMP GET /edge/cmp?{params} /edge/cmp?down_pressure_kpa=20&pattern_density=0.5 outputs (blanket_removal_rate_nm_min, time_to_clear_s, planarization_efficiency_pct, dishing_nm, erosion_nm, verdict), profile.step_curve & profile.surface.
Interconnect GET /edge/interconnect?{params} /edge/interconnect?wire_width_nm=20&current_density_ma_cm2=8 outputs (effective_resistivity_uohm_cm, resistivity_ratio, rc_delay_ps, em_mttf_years, em_margin, verdict), profile.resistivity_curve & profile.geometry.
Thermal GET /edge/thermal?{params} /edge/thermal?die_power_w=700&hotspot_power_frac=0.35 outputs (thermal_resistance_ja_c_w, silicon_conductivity_w_mk, junction_temp_uniform_c, junction_temp_hotspot_c, hotspot_delta_c, thermal_margin_c, verdict), profile.stack & profile.lateral.
Transistor GET /edge/transistor?{params} /edge/transistor?gate_length_nm=16&gate_config=4 outputs (natural_length_nm, subthreshold_swing_mv_dec, dibl_mv_v, vt_eff_v, ion_ua_um, ioff_na_um, ion_ioff_ratio, transconductance_us_um, intrinsic_delay_ps, verdict), profile.transfer & profile.output.
Yield GET /edge/yield?{params} /edge/yield?die_width_mm=26&die_height_mm=33&defect_density_d0=0.12 outputs (die_area_mm2, gross_die_per_wafer, defects_per_die, yield_percent, good_die_per_wafer, packing_efficiency_percent, cost_per_good_die_usd, yield_poisson_percent, yield_murphy_percent, yield_negbinom_percent, yield_seeds_percent, verdict), profile.yield_curve & profile.wafer.
SRAM POST /edge/sram /edge/sram?vdd=0.8&cell_ratio=1.5&pull_up_ratio=1.0&array_mbit=32 outputs (snm_hold_mv, snm_read_mv, write_margin_mv, trip_point_v, snm_read_worstcase_mv, sigma_target, snm_read_sigma_mv, vmin_v, read_snm_ratio_percent, writable, verdict), profile.vtc_hold, profile.vtc_read, profile.snm_vs_cell_ratio & profile.wwm_vs_pullup_ratio.
Systolic Array POST /edge/systolic /edge/systolic?rows=128&cols=128&gemm_m=2048&gemm_k=8192&gemm_n=8192 outputs (peak_tops, achieved_tops, pe_utilization_percent, map_efficiency_percent, temporal_efficiency_percent, arithmetic_intensity, ridge_point_flop_byte, bottleneck, latency_ms, hbm_traffic_gb, tile_working_set_mb, sram_fits, tops_per_watt, power_w, verdict), profile.roofline & profile.util_vs_dim.
HBM Bandwidth POST /edge/hbm /edge/hbm?num_stacks=6&data_rate_gbps=6.4&model_params_b=70&batch=1 outputs (peak_bandwidth_gbs, effective_bandwidth_gbs, dram_efficiency_percent, row_efficiency_percent, rw_efficiency_percent, refresh_efficiency_percent, channels, per_channel_gbs, page_hit_latency_ns, random_latency_ns, model_size_gb, arithmetic_intensity, time_per_token_ms, decode_tokens_per_s, power_w, gbs_per_watt, verdict), profile.bw_vs_access & profile.bw_vs_hit.
KV Cache / Attention POST /edge/kvcache /edge/kvcache?model_params_b=8&num_layers=32&context_length=8192&batch=32 outputs (kv_bytes_per_token, kv_kb_per_token, kv_per_sequence_gb, kv_total_gb, weight_gb, footprint_gb, capacity_gb, utilization_percent, kv_fraction_percent, free_for_kv_gb, fits, max_batch_at_context, max_context_at_batch, bytes_per_step_gb, time_per_step_ms, decode_tokens_per_s, bottleneck, verdict), profile.footprint_vs_ctx & profile.tps_vs_ctx.
LLM Training Memory POST /edge/training /edge/training?model_params_b=8&num_gpus=8&seq_length=4096&zero_stage=3 outputs (model_states_unsharded_gb, model_states_per_gpu_gb, activations_per_gpu_gb, per_gpu_total_gb, gpu_capacity_gb, utilization_percent, fits, bytes_per_param, weights_per_gpu_gb, grads_per_gpu_gb, optimizer_per_gpu_gb, min_gpus_to_fit, aggregate_cluster_gb, global_batch, zero_stage, checkpointing, verdict), profile.mem_vs_gpus & profile.mem_vs_seq.
POST /edge/power /edge/power?transistor_count_b=20&core_voltage_v=0.85&clock_ghz=2.0&tdp_w=700 outputs (dynamic_power_w, logic_dynamic_w, interconnect_power_w, leakage_power_w, total_power_w, junction_temp_c, tjmax_c, tdp_w, power_density_w_mm2, leakage_fraction_percent, within_tdp, within_tjmax, thermal_runaway, max_clock_ghz, energy_per_cycle_nj, gops_per_w, verdict), profile.power_vs_freq & profile.power_vs_volt.
POST /edge/parallelism /edge/parallelism?model_params_b=70&num_gpus=64&tensor_parallel=8&pipeline_parallel=4 outputs (data_parallel, used_gpus, idle_gpus, valid_layout, tokens_per_step, compute_time_ms, tp_comm_ms, pp_comm_ms, pipeline_bubble_ms, dp_allreduce_ms, dp_allreduce_raw_ms, step_time_ms, comm_fraction_percent, bubble_fraction_percent, scaling_efficiency_percent, mfu_percent, achieved_tflops_per_gpu, throughput_tokens_s, per_gpu_tokens_s, bottleneck, verdict), profile.eff_vs_gpus & profile.eff_vs_bw.
POST /edge/reliability /edge/reliability?vdd_v=0.8&temperature_c=85&vth_budget_mv=60&target_lifetime_yr=10 outputs (dvth_bti_mv, dvth_hci_mv, dvth_total_mv, guardband_mv, freq_degradation_percent, tau_bti_yr, tau_hci_yr, tau_tddb_yr, wearout_life_yr, mttf_years, dominant_mechanism, meets_target, oxide_field_mv_cm, verdict), profile.degradation & profile.life_vs_v.
POST /edge/placeroute /edge/placeroute?instance_count_k=500&rent_exponent=0.6&utilization_target=70&metal_layers=10 outputs (core_area_mm2, die_w_um, die_h_um, utilization_percent, total_instances, total_nets, avg_net_length_um, total_wirelength_m, routing_demand_m, routing_supply_m, congestion_percent, routing_overflow, signal_layers, logic_delay_ns, interconnect_delay_ns, critical_path_ns, fmax_ghz, required_period_ns, slack_ns, timing_met, detour_factor, dominant_limiter, verdict), profile.cong_vs_util & profile.fmax_vs_util.
POST /edge/pdn /edge/pdn?current_a=120&pdn_inductance_ph=8&decap_uf=80&voltage_margin_mv=60 outputs (ir_drop_mv, transient_droop_mv, total_droop_mv, droop_percent, vmin_mv, margin_mv, meets_margin, z0_mohm, z_peak_mohm, q_factor, damping_zeta, f_res_mhz, target_impedance_mohm, meets_z_target, decap_needed_uf, edge_factor, current_step_a, dominant_component, verdict), profile.droop_vs_decap & profile.impedance_vs_freq.
POST /edge/quantization /edge/quantization?weight_bits=4&activation_bits=16&kv_bits=16&group_size=128 outputs (format, effective_weight_bits, scale_overhead_percent, weight_gb, kv_cache_gb, total_gb, fp16_total_gb, memory_reduction_x, decode_tokens_s, fp16_decode_tokens_s, decode_speedup_x, compute_speedup_x, decode_bottleneck, sqnr_weight_db, sqnr_activation_db, sqnr_kv_db, min_sqnr_db, quant_error_percent, accuracy_retention_percent, error_source, verdict), profile.acc_vs_bits & profile.tps_vs_bits.
POST /edge/flashattention /edge/flashattention?seq_length=32768&head_dim=128&causal=1&block_size=128 outputs (format, achieved_block, max_block_sram, sram_needed_kb, sram_used_kb, sram_budget_kb, sram_fit, q_blocks, kv_blocks, flops_gflop, scores_matrix_gb, naive_hbm_gb, fa_hbm_gb, hbm_reduction_x, machine_balance_flop_byte, arithmetic_intensity_fa, arithmetic_intensity_naive, fa_bottleneck, naive_bottleneck, naive_time_ms, fa_time_ms, compute_time_ms, speedup_x, fa_tflops, fa_util_percent, verdict), profile.reduction_vs_seq & profile.speedup_vs_seq.
POST /edge/moe /edge/moe?num_experts=64&top_k=2&capacity_factor=1.25&expert_parallel=8 outputs (format, tokens, routed_assignments, mean_load_per_expert, capacity_per_expert, dropped_tokens, drop_percent, padding_waste_percent, slot_utilization_percent, total_expert_params_b, active_params_b, sparsity_percent, expert_weights_gb, moe_tflop, dense_equiv_tflop, compute_savings_x, all2all_gb, compute_time_ms, all2all_time_ms, step_time_ms, comm_fraction_percent, bottleneck, achieved_tflops, mfu_percent, verdict), profile.drop_vs_capacity, profile.waste_vs_capacity & profile.expert_loads.
POST /edge/electromigration /edge/electromigration?wire_current_ma=0.15&wire_width_nm=100&temperature_c=105&target_lifetime_years=10 outputs (current_density_ma_cm2, cross_section_nm2, mttf_years, is_immortal, meets_lifetime, jmax_ma_cm2, j_headroom_percent, imax_ma, blech_length_um, blech_product_a_cm, blech_immortal, acceleration_factor, fit_rate, temperature_k, dominant_component, verdict), profile.mttf_vs_j & profile.jmax_vs_temp.
POST /edge/clocktree /edge/clocktree?clock_freq_mhz=1200&tree_depth=8&process_variation_pct=6&mesh_enable=0 outputs (period_ps, insertion_delay_ps, systematic_skew_ps, random_skew_ps, total_skew_ps, skew_percent, random_jitter_rms_ps, jitter_pk_pk_ps, jitter_percent, clock_uncertainty_ps, uncertainty_percent, uncertainty_budget_ps, useful_period_ps, headroom_percent, meets_budget, fmax_mhz, n_buffers, total_wire_mm, clock_cap_pf, clock_power_w, dominant_component, topology, verdict), profile.uncertainty_vs_freq & profile.skew_vs_depth.
POST /edge/noc /edge/noc?mesh_radix_k=8&torus_enable=0&injection_rate=0.15&router_stages=3 outputs (num_nodes, avg_hops, diameter_hops, zero_load_latency_ns, avg_latency_ns, serialization_latency_ns, hop_latency_ns, queueing_latency_ns, load_percent, saturation_injection_rate, accepted_injection_rate, routing_efficiency_percent, flit_bytes, link_bandwidth_gbps, bisection_channels, bisection_bandwidth_gbps, injected_bw_per_node_gbps, aggregate_throughput_gbps, meets_budget, latency_headroom_percent, dominant_component, topology, verdict), profile.latency_vs_load & profile.sat_vs_radix.
POST /edge/warpage /edge/warpage?total_power_w=350&tj_max_c=105&substrate_size_mm=55&warpage_balance_factor=0.82 outputs (theta_ja_c_w, r_tim1_c_w, r_lid_c_w, r_tim2_c_w, r_sink_c_w, junction_temp_c, thermal_headroom_c, meets_thermal, dominant_thermal_resistor, delta_cte_ppm, delta_temp_c, curvature_1_m, raw_warpage_um, net_warpage_um, warpage_headroom_percent, meets_warpage, warpage_shape, meets_budget, verdict), profile.tj_vs_power & profile.warp_vs_temp.
POST /edge/photonics /edge/photonics?laser_power_dbm=10&data_rate_gbps=100&num_wavelengths=8&modulation_format=PAM4 outputs (total_insertion_loss_db, modulator_loss_db, coupling_loss_total_db, waveguide_loss_db, fiber_loss_db, wdm_loss_db, dominant_loss, received_power_dbm, q_factor, symbol_rate_gbaud, receiver_sensitivity_dbm, link_margin_db, meets_link, aggregate_bandwidth_gbps, aggregate_bandwidth_tbps, laser_electrical_mw, driver_electrical_mw, total_electrical_mw, laser_power_fraction_pct, energy_per_bit_pj, meets_energy, meets_budget, verdict), profile.margin_vs_reach & profile.margin_vs_rate. Aliases: /edge/siliconphotonics, /edge/copackagedoptics, /edge/cpo, /edge/opticalio, /edge/opticallink, /edge/wdm.
POST /edge/cooling /edge/cooling?tdp_w=700&cooling_mode=cold_plate&flow_rate_lpm=2&tj_max_c=105 outputs (theta_ja_c_w, r_tim1_c_w, r_lid_c_w, r_tim2_c_w, r_plate_c_w, r_conduction_c_w, r_convection_c_w, r_caloric_c_w, dominant_resistance, junction_temp_c, tj_headroom_c, meets_thermal, coolant_rise_c, coolant_outlet_c, flow_display, flow_unit, mass_flow_kg_s, film_coeff_w_m2k, wetted_area_cm2, pressure_drop_kpa, pump_power_w, cooling_overhead_pct, meets_efficiency, meets_budget, verdict), profile.tj_vs_flow & profile.tj_vs_tdp. Aliases: /edge/coldplate, /edge/liquidcooling, /edge/heatsink, /edge/immersion, /edge/twophase, /edge/coolingloop, /edge/datacentercooling.
POST /edge/specdec /edge/specdec?gamma=4&alpha=0.8&draft_params_b=1&target_params_b=70 outputs (format, expected_tokens_per_step, max_tokens_per_step, block_efficiency_percent, acceptance_percent, speedup_x, baseline_tokens_s, spec_tokens_s, target_decode_ms, draft_step_ms, draft_total_ms, verify_step_ms, spec_step_ms, draft_cost_ratio, draft_overhead_percent, verify_fraction_percent, verify_bottleneck, verify_mem_ms, verify_compute_ms, target_bound, optimal_gamma, optimal_speedup_x, verdict), profile.speedup_vs_gamma, profile.tokens_vs_gamma & profile.speedup_vs_alpha.
POST /edge/chiplet /edge/chiplet?die_area_mm2=800&num_chiplets=4&packaging_type=3 outputs (format, packaging, chiplet_area_mm2, gross_die_mono, gross_die_chiplet, mono_yield_percent, chiplet_yield_percent, kgd_yield_percent, assembly_yield_percent, system_yield_percent, mono_cost_per_good_usd, silicon_cost_usd, package_cost_usd, chiplet_cost_per_good_usd, savings_x, shoreline_mm, avail_d2d_bw_tbps, bw_utilization_percent, beachfront_limited, d2d_energy_pj_bit, d2d_power_w, link_power_penalty_w, stack_thermal_rise_c, optimal_n, optimal_savings_x, verdict), profile.savings_vs_n, profile.yield_vs_n & profile.savings_vs_d0.
POST /edge/cache /edge/cache?working_set_mb=96&l1_kb=64&l2_kb=1024&l3_mb=32 outputs (format, working_set_fits_in, l1_hit_percent, l2_local_hit_percent, l3_local_hit_percent, overall_hit_percent, miss_to_memory_percent, amat_ns, amat_cycles, amat_l1_ns, amat_l2_ns, amat_l3_ns, amat_mem_ns, l1_mpki, llc_mpki, stall_cpi, effective_cpi, slowdown_x, bw_demand_gb_s, bw_util_percent, eff_mem_bw_gb_s, mlp_needed_per_core, l3_enabled, verdict), profile.hitrate_vs_capacity, profile.amat_vs_ws & profile.amat_vs_locality. Aliases: /edge/amat, /edge/cachehierarchy, /edge/memoryhierarchy, /edge/llc, /edge/missrate, /edge/mpki.
POST /edge/serdes /edge/serdes?data_rate_gbps=112&modulation=2&channel_type=1&reach_mm=20 outputs (format, modulation, channel, baud_gbd, nyquist_ghz, insertion_loss_db, rx_swing_mv, eye_height_mv, eye_open_percent, crosstalk_rms_mv, isi_rms_mv, noise_rms_mv, q_factor, q_required, raw_ber, post_fec_ber, fec_coding_gain_db, margin_db, loss_budget_db, link_closes, pj_per_bit, per_lane_power_w, aggregate_gbps, aggregate_tbps, total_power_w, max_lanes_shoreline, shoreline_use_percent, beachfront_limited, bw_density_gbps_per_mm, edge_bw_tbps, optimal_rate_gbps, verdict), profile.margin_vs_stdrate, profile.loss_vs_reach, profile.margin_vs_reach & profile.margin_vs_rate. Aliases: /edge/ucie, /edge/pam4, /edge/linkbudget, /edge/signalintegrity, /edge/eye, /edge/lane.

Every simulator parameter is an optional query argument — omit any and a sensible default is used. Responses are plain JSON with permissive access, so you can pipe them straight into a notebook, an agent tool, or an auto-programming pipeline.

Reports we generate · machine-readable output for every run
📄
Per-run simulation report

Each simulation returns a structured JSON report — the model name, the exact inputs used, every computed output metric, and a numeric profile curve — ready to log, diff, or chart.

🛰️
Edge node test-results report

The /edge/ dashboard reports live execution results per node across the seven-machine pool, so you can see which nodes ran your workload and confirm failover health.

📚
CFSGPT structured answer

Knowledge queries return a formatted report — narrative prose with bold lead-ins, styled comparison tables, hand-authored SVG diagrams, and rendered KaTeX math.

Flagship keywords · curated CFSGPT knowledge
Flagship keywords · every curated, diagram-rich answer we have authored

Beyond the live tools, ChipFoundryServices ships a hand-authored knowledge base of flagship answers — each one renders with styled comparison tables, real engineering diagrams, and typeset math. Tap any keyword to ask CFSGPT and see the full answer inline. These are the curated flagships across the AI-chip stack; the wider base holds 13,000+ entries.

Design & Architecture
Process & Equipment
Lithography & Computational
Packaging & Integration
AI · ML · DL · Transformers

Each keyword resolves to a full flagship answer — narrative prose with bold lead-ins, styled comparison tables, hand-authored SVG diagrams, and rendered KaTeX math. Every answer is also callable as raw JSON at /api.php?q={keyword}.

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