Model a stacked High-Bandwidth Memory subsystem — the HBM3/HBM3E stacks that feed a GPU or AI accelerator — then run it: the simulation executes on the ChipFoundryServices distributed compute pool. From the stack geometry (stacks × bus width × per-pin data rate) it computes the peak bandwidth, then the effective bandwidth the controller actually delivers after DRAM efficiency losses — row-buffer page misses, read/write bus turnaround, and refresh — reports page-hit and random access latency, and rolls it up to the headline number: the memory-bound LLM decode token rate. Autoregressive decode streams the whole weight tensor once per token, so throughput tracks bandwidth, not FLOPs — which is why HBM is the scarce resource in AI inference. Reduced-order educational model. See also the systolic array, transistor I-V, thermal, interconnect RC, die-yield, 6T SRAM, CMP planarization and lithography simulators and the compute-pool status.
curl -X POST https://www.chipfoundryservices.com/edge/hbm \
-H "Content-Type: application/json" \
-d '{"num_stacks":6,"bus_width_bits":1024,"data_rate_gbps":6.4,
"row_hit_rate":60,"read_pct":70,"banks":16,"access_bytes":256,
"model_params_b":70,"precision_bits":16,"batch":1}'
Returns JSON with outputs (peak_bandwidth_gbs, effective_bandwidth_gbs,
dram_efficiency_percent, row_efficiency_percent, rw_efficiency_percent, refresh_efficiency_percent,
channels, per_channel_gbs, page_hit_latency_ns, random_latency_ns, model_size_gb, arithmetic_intensity,
time_per_token_ms, decode_tokens_per_s, power_w, gbs_per_watt, verdict), the full
profile (48-point bw_vs_access and bw_vs_hit sweeps, plus
peak_bw, eff_bw, row_eff, rw_eff,
dram_eff), the serving node, and compute_ms. Endpoint aliases
/edge/bandwidth, /edge/dram, /edge/memory.