Chip Thermal & Hotspot Junction-Temperature Simulator

Set a die power, geometry and cooling stack and run it — the simulation executes on the ChipFoundryServices distributed compute pool and solves the self-consistent junction-to-ambient thermal-resistance ladder (with temperature-dependent silicon conductivity), then adds a hotspot-spreading model to find the peak junction temperature, the thermal margin against Tj,max, and whether the part throttles. Power density, not transistor count, now sets the cooling budget. Reduced-order educational model. See also the interconnect RC, CMP planarization, plasma-etch and lithography simulators and the compute-pool status.

700 W GPU Mobile SoC Liquid-metal TIM
Junction-to-ambient stack — band height ∝ thermal resistance, colored by temperature
Lateral junction temperature — hotspot peak vs the Tj,max limit
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/thermal \
  -H "Content-Type: application/json" \
  -d '{"die_power_w":300,"die_size_mm":20,"die_thickness_um":250,
       "hotspot_power_frac":0.25,"hotspot_area_frac":0.05,
       "tim_conductivity_w_mk":5.0,"heatsink_resistance_c_w":0.15,"ambient_c":25}'
Returns JSON with outputs (junction-to-ambient resistance, silicon/TIM/heatsink resistances, temperature-dependent silicon conductivity, uniform and hotspot junction temperature, hotspot delta, average and peak power density, thermal margin, verdict), the full profile (per-layer resistance stack, 181-point lateral temperature profile, geometry), the serving node, and compute_ms.