Interconnect RC Delay & Electromigration Simulator

Set a copper back-end-of-line (BEOL) wire geometry and run it — the simulation executes on the ChipFoundryServices distributed compute pool and returns the size-effect resistivity rise, the distributed-line 50% RC signal delay, and the Black's-equation electromigration lifetime that bounds how much current the wire survives. Below ~40 nm the wire, not the transistor, sets the clock. Reduced-order educational model. See also the CMP planarization, plasma-etch, deposition and lithography simulators and the compute-pool status.

2nm local Global clock Power rail
Copper size-effect — effective resistivity ρ/ρ₀ vs wire width
Wire cross-section — conductive core, barrier liner, neighbor coupling
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/interconnect \
  -H "Content-Type: application/json" \
  -d '{"wire_width_nm":20,"aspect_ratio":2.0,"wire_length_um":100,
       "pitch_nm":40,"barrier_thickness_nm":2.0,
       "current_density_ma_cm2":1.0,"temperature_c":90,"dielectric_k":2.7}'
Returns JSON with outputs (effective resistivity, resistance, capacitance, RC delay, EM MTTF and margin, max current density, verdict), the full profile (resistivity size-effect curve, delay-vs-length curve, cross-section geometry), the serving node, and compute_ms.