EDA Place-and-Route Simulator

Model whether a block routes clean and closes timing — then run it: the simulation executes on the ChipFoundryServices distributed compute pool. Place-and-route turns a netlist into geometry, and two forces fight over the floorplan. Wirelength follows Rent's rule: the average net grows as ⟨L⟩ ∝ N(p−0.5) with the Rent exponent p and the standard-cell pitch, so a bigger, more-connected design has longer wires. Routing congestion is the ratio of that demand to the track supply the metal stack provides — supply ∝ (core area / pitch) × signal layers — and when demand approaches supply the router detours. Timing walks a logic + interconnect critical path; denser packing shortens wires and helps timing until congestion forces detours and it turns around, so there is a density sweet spot. The node sweeps placement utilization and returns the congestion, the maximum clock frequency Fmax, the timing slack and the dominant limiter — the same wirelength, metal-layer and routing-pitch trade-offs that decide whether a block tapes out at the datacenter, GPU-block and congested corners. Reduced-order educational model. See also the device reliability, transistor I-V, power & thermal, thermal, interconnect RC/EM, 6T SRAM, die-yield, 3D-parallelism, HBM bandwidth, systolic array, CMP planarization and lithography simulators and the compute-pool status.

curl -X POST https://www.chipfoundryservices.com/edge/placeroute \
  -H "Content-Type: application/json" \
  -d '{"instance_count_k":500,"avg_fanout":3,"rent_exponent":0.6,
       "utilization_target":70,"aspect_ratio":1.0,"metal_layers":10,
       "cell_area_um2":0.30,"clock_ghz":1.5,"routing_pitch_nm":80}'