Chip Power & Thermal-Budget Simulator

Model where a processor’s watts go — then run it: the simulation executes on the ChipFoundryServices distributed compute pool. Every switching transistor burns dynamic power ≈ activity × C × V² × f — quadratic in voltage, linear in clock — and the wires add interconnect power on top. But the design also leaks: static leakage rises with temperature and doubles roughly every 15 °C, so leakage heats the die, which raises leakage further. The node solves that junction-temperature fixed point (Tj = ambient + θJA × Ptotal), checks the design against its TDP and Tjmax, flags thermal runaway when the leakage–temperature loop diverges, and finds the headline number: the thermal-limited maximum clock the cooling solution can sustain. These are the same dynamic-vs-leakage and voltage-vs-frequency trade-offs that set an AI accelerator’s power envelope. Reduced-order educational model. See also the training-memory, KV-cache, HBM bandwidth, systolic array, transistor I-V, thermal, interconnect RC, die-yield, 6T SRAM, CMP planarization and lithography simulators and the compute-pool status.

Data-center GPU · 700 W Mobile SoC · low-V Leakage runaway
Total power vs clock frequency — dynamic power climbs linearly with clock, so raising the frequency drives the design toward its TDP ceiling (dashed red). Your operating clock (●) sits on the curve; the vertical marker is the thermal-limited max clock — the fastest the cooling solution can sustain under Tjmax and TDP
Left: total power vs core voltage — dynamic power is quadratic in voltage, so voltage is the biggest lever (dashed line = TDP). Right: the power budget — logic dynamic + interconnect + leakage as a share of TDP, and junction temperature as a share of Tjmax. Marker is your operating voltage
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/power \
  -H "Content-Type: application/json" \
  -d '{"transistor_count_b":20,"core_voltage_v":0.85,"clock_ghz":2.0,
       "activity_factor":0.15,"cap_per_transistor_ff":0.10,"interconnect_fraction":0.4,
       "die_area_mm2":600,"leakage_density_w_mm2":0.015,
       "thermal_resistance_c_w":0.06,"tdp_w":700}'
Returns JSON with outputs (dynamic_power_w, logic_dynamic_w, interconnect_power_w, leakage_power_w, total_power_w, junction_temp_c, tjmax_c, tdp_w, power_density_w_mm2, leakage_fraction_percent, within_tdp, within_tjmax, thermal_runaway, max_clock_ghz, energy_per_cycle_nj, gops_per_w, verdict), the full profile (48-point power_vs_freq and power_vs_volt sweeps, plus dynamic_w, leakage_w, tdp_w, total_w, clock_ghz, core_voltage_v, junction_temp_c, within_tdp), the serving node, and compute_ms. Endpoint aliases /edge/powerbudget, /edge/tdp, /edge/dvfs, /edge/leakage.