Clock-Tree Skew & Jitter Simulator

Model whether a clock can close timing across a whole die — then run it: the simulation executes on the ChipFoundryServices distributed compute pool. A clock fanned out to millions of flip-flops does not arrive everywhere at once. Skew is the spatial spread: a systematic part from unbalanced path length (RC the tree failed to match) plus a random part from on-chip variation — each buffer stage delay drifts by σ, so over D stages two paths diverge like √(2D)·σ and over N sinks the worst pair is √(2·ln N)·σ out. Jitter is the temporal wander: supply noise modulates buffer delay (random jitter, √D accumulation) and duty-cycle distortion adds a deterministic floor, with peak-to-peak ≈ 14.07·rms + DJ at BER 10−12. The clock uncertainty skew + jitter is subtracted from the period; when it exceeds the timing-closure budget the design cannot reach frequency. A mesh shorts sinks together and averages out the systematic skew at the cost of extra switched capacitance. Reduced-order educational model. See also the place-and-route, power-delivery network, electromigration, interconnect RC, device reliability, SerDes link, transistor I-V, power & thermal, thermal and lithography simulators and the compute-pool status.

Mobile SoC High-perf CPU Mesh · AI accelerator
Clock uncertainty (skew + jitter) as a share of the period vs clock frequency. Skew and jitter are fixed in picoseconds, so as frequency rises the period shrinks and the uncertainty fraction climbs. It crosses the dashed red budget at fmax (dashed amber); the marker (●) is your operating frequency
Left: total skew vs tree depth — random OCV skew accumulates like √(2D), so deeper trees spread more (marker ● = your depth). Right: the uncertainty budget — skew, jitter and their sum as a share of the timing budget (100 % = at the edge; the sum over 100 % is a violation)
Developer API — same simulation over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/clocktree \
  -H "Content-Type: application/json" \
  -d '{"clock_freq_mhz":1200,"num_sinks":80000,"die_size_mm":15,"tree_depth":10,
       "buffer_delay_ps":22,"wire_rc_ps_per_mm":55,"process_variation_pct":6,
       "supply_noise_pct":4,"wire_mismatch_pct":5,"duty_distortion_ps":6,
       "clock_fanout":4,"uncertainty_budget_pct":15,"mesh_enable":0}'
Returns JSON with outputs (period_ps, insertion_delay_ps, systematic_skew_ps, random_skew_ps, total_skew_ps, skew_percent, random_jitter_rms_ps, jitter_pk_pk_ps, jitter_percent, clock_uncertainty_ps, uncertainty_percent, uncertainty_budget_ps, useful_period_ps, headroom_percent, meets_budget, fmax_mhz, n_buffers, total_wire_mm, clock_cap_pf, clock_power_w, dominant_component, topology, verdict), the full profile (48-point uncertainty_vs_freq sweep [freq_mhz, uncertainty_percent] and 48-point skew_vs_depth sweep [tree_depth, total_skew_ps]), the serving node, and compute_ms. Endpoint aliases /edge/cts, /edge/clockskew, /edge/skew, /edge/clockjitter, /edge/jitter, /edge/clocktreesynthesis.