Transformer-Chip Inference Simulator

Pair an AI accelerator with a transformer model and predict LLM serving performance: decode throughput and latency, time-to-first-token, the roofline memory-vs-compute bottleneck, KV-cache footprint, and the throughput-vs-batch curve whose knee is the memory→compute transition. Runs on the ChipFoundryServices distributed compute pool. Reduced-order educational model. See also the etch and deposition simulators and the compute-pool status.

H100 · Llama-70B H100 · 70B fp8 H200 · 70B H100 · Llama-8B
Accelerator
Transformer model
Workload
Developer API — same model over HTTP (load-balanced across the pool): 
curl -X POST https://www.chipfoundryservices.com/edge/infer \
  -H "Content-Type: application/json" \
  -d '{"peak_tflops":990,"hbm_bw_gbs":3350,"hbm_cap_gb":80,"params_b":70,
       "hidden_dim":8192,"layers":80,"n_heads":64,"n_kv_heads":8,
       "seq_len":4096,"batch":1,"weight_bytes":2}'
Returns JSON with outputs (decode/prefill throughput, latency, bottleneck, arithmetic intensity, utilization, memory footprint), the profile.batch_curve, the serving node, and compute_ms.