Chiplet & Advanced Packaging Simulator

Model when splitting a giant monolithic accelerator die into chiplets pays off — then run it: the simulation executes on the ChipFoundryServices compute pool. Defect-limited yield is super-linear in die area — random particle defects at density D0 kill any die they land on, so a reticle-sized SoC (the clustered negative-binomial law Y = (1 + A·D0/alpha)-alpha) can yield below 50%. Disaggregation cuts the design into N smaller chiplets that each yield far better — but you now pay for a package that wires them back together, lose parts at assembly, and burn energy shuttling bits across die boundaries. Chiplets are tested first (known-good-die): coverage t catches most bad dies, but escapes get built into a package and scrap the whole unit. System yield = KGD × assembly. Each packaging class — organic MCM, EMIB silicon bridge, CoWoS interposer, 3D hybrid bond — sets the die-to-die bandwidth density (GB/s per mm of shoreline) and the energy per bit. The node returns the monolithic-vs-chiplet cost per good part, the system yield, the beachfront bandwidth and interconnect power, the optimal chiplet count, and the operating regime. Reduced-order educational model. See also the speculative-decoding, Mixture-of-Experts, FlashAttention, quantization, KV-cache, HBM bandwidth, systolic array, 3D-parallelism, power & thermal, transistor I-V, thermal, die-yield and lithography simulators and the compute-pool status.

AMD MI300-class EPYC 8-chiplet Small monolith 3D hybrid bond
Cost-per-good-part savings vs chiplet count N. Each bar is how much cheaper the disaggregated design is than one monolithic die: it rises as smaller chiplets yield better, then flattens or falls once packaging, assembly loss and known-good-die escapes pile up. The dashed line marks (break-even) and ▯ marks your N; the tallest bar is the optimal N
Left: savings vs defect density D0 — chiplets win harder as wafers get dirtier and big dies yield worse (▯ marks your D0). Right: the yield & cost budget — monolithic vs chiplet per-die yield, the system yield after KGD and assembly, and the die-to-die shoreline bandwidth utilization
Developer API — same simulation over HTTP (load-balanced across the pool):
curl -X POST https://www.chipfoundryservices.com/edge/chiplet \
  -H "Content-Type: application/json" \
  -d '{"die_area_mm2":800,"num_chiplets":4,"defect_density_d0":0.10,
       "clustering_alpha":3,"packaging_type":3,"kgd_coverage":0.95,
       "assembly_yield_join":0.998,"d2d_traffic_tbps":2,"wafer_cost_usd":16000}'
Returns JSON with outputs (format, packaging, chiplet_area_mm2, gross_die_mono, gross_die_chiplet, mono_yield_percent, chiplet_yield_percent, kgd_yield_percent, assembly_yield_percent, system_yield_percent, mono_cost_per_good_usd, silicon_cost_usd, package_cost_usd, chiplet_cost_per_good_usd, savings_x, shoreline_mm, avail_d2d_bw_tbps, bw_utilization_percent, beachfront_limited, d2d_energy_pj_bit, d2d_power_w, link_power_penalty_w, stack_thermal_rise_c, optimal_n, optimal_savings_x, verdict), the full profile (16-point savings_vs_n and yield_vs_n sweeps, 48-point savings_vs_d0 sweep, plus num_chiplets, optimal_n, savings_x, system_yield_percent, mono_yield_percent, chiplet_yield_percent, bw_utilization_percent, d2d_power_w), the serving node, and compute_ms. Endpoint aliases /edge/chiplets, /edge/packaging, /edge/disaggregation, /edge/cowos, /edge/interposer, /edge/d2d.