2D Material Transistors

# Two-Dimensional (2D) Material Transistors: Physics, Materials & Scaling

Two-Dimensional (2D) Material Transistors represent the ultimate channel-scaling frontier for semiconductor logic, providing an atomically thin, chemically pristine platform designed to extend transistor scaling into the sub-1 nm (Angstrom-era) regime where conventional bulk and nanosheet silicon reach their fundamental electrostatic and quantum mechanical limits. Built from monolayer transition metal dichalcogenides (TMDs) such as molybdenum disulfide ($\text{MoS}_2$), tungsten diselenide ($\text{WSe}_2$), and tungsten disulfide ($\text{WS}_2$), 2D semiconductors possess an atomically precise channel thickness ($t_{ch} = 0.65\text{ to }0.70\,\text{nm}$) completely free of out-of-plane dangling bonds.

In standard silicon gate-all-around (GAA) nanosheets, thinning the silicon body below $3\,\text{nm}$ causes severe degradation in electron mobility ($\mu$) due to severe surface-roughness scattering and quantum confinement-induced bandgap opening. In contrast, monolayer TMDs feature natural van der Waals (vdW) surfaces that exhibit no dangling surface bonds, low out-of-plane dielectric constants ($\kappa_\perp \approx 4\text{ to }7$), and a direct electronic bandgap ($E_g \approx 1.8\text{ to }2.0\,\text{eV}$). These properties yield an unprecedented electrostatic scale length ($\lambda \le 1.0\,\text{nm}$), enabling gate length scaling down to $L_g \le 5\,\text{nm}$ with virtually zero drain-induced barrier lowering (DIBL) and steep subthreshold switching.

Crystal Lattice & Device Architecture of Monolayer MoS₂ FET atomic trigonal prismatic structure (1H phase) and dual-gate device integration with semi-metallic contacts 1. MONOLAYER MoS₂ LATTICE (1H PHASE) Top Sulfur (S) Molybdenum (Mo) Bottom Sulfur (S) 0.65 nm Crystal & Electronic Properties: • Coordination: Trigonal Prismatic (1H Phase) • In-plane Lattice Constant: a = 3.16 Å • Monolayer Physical Thickness: t_ch = 0.65 nm • Surface State: Zero out-of-plane dangling bonds • Bandgap: Direct 1.85 eV (Monolayer vs 1.29 eV bulk) • Dielectric Permittivity: κ_⊥ = 4.0 (Suppresses DIBL) • Effective Mass: m* = 0.55 m₀ (High density of states) • Quantum Capacitance: C_Q > 3.0 μF/cm² (No DOS bottleneck) 2. DUAL-GATE 2D FET INTEGRATION Top Gate (TiN / W) Top Dielectric: HfO₂ (EOT = 0.8 nm) Source (Bi) Monolayer MoS₂ Channel (t_ch = 0.65 nm) Drain (Bi) Bottom Dielectric: HfO₂ / h-BN Back Gate Electrode Advanced 2D Integration Innovations: • Semi-Metallic Bi/Sb Contacts: Eliminates Fermi-level pinning & gap states (MIGS); Delivers zero Schottky barrier (Φ_SB ≈ 0, R_c < 120 Ω·μm). • Dielectric Nucleation Engineering: Pristine basal plane lacks dangling bonds for ALD. Requires molecular seeding (Al oxidized sub-monolayer). • Complementary 2D CMOS Pair: nMOS: Monolayer MoS₂ (I_on > 1000 μA/μm) pMOS: Monolayer WSe₂ / PtSe₂ (I_on > 600 μA/μm)

---

## 1. Physics of Electrostatic Scale Length: Why 2D Beats Silicon

The fundamental physics governing short-channel effect (SCE) immunity in ultra-scaled field-effect transistors is described by the natural electrostatic scale length ($\lambda$).

Natural Electrostatic Scale Length & Gate Scaling Limits quantitative comparison of electrostatic scale length (λ) and minimum gate length (L_g,min) across technologies SCALE LENGTH (λ) vs. CHANNEL THICKNESS 5 nm 4 nm 3 nm 2 nm 1 nm Scale Length λ (nm) → 1 3 6 10 14 Channel Thickness t_ch (nm) → Si Limit (t=3nm, λ=2.1nm) Bulk Si / FinFET MoS₂ Monolayer (t=0.65nm, λ=0.58nm) 2D materials cut scale length by >70% vs. Silicon PHYSICAL SCALING BOUNDARIES ARCHITECTURE t_ch λ_DG L_g,min FinFET (Bulk Si) 6.0 nm 3.4 nm 15 nm Si GAA Nanosheet 4.0 nm 2.2 nm 10 nm Si Forksheet FET 3.5 nm 2.1 nm 9 nm 2D Monolayer MoS₂ 0.65 nm 0.58 nm 2.6–4 nm Classical Scale Length Criterion: λ_DG = √[ (ε_ch / 2ε_ox) · t_ch · t_ox ] L_g,min ≥ 4.5 · λ_DG (for DIBL < 50 mV/V) Why 2D TMD Outperforms Sub-3nm Silicon: • Ultrathin t_ch = 0.65 nm minimizes channel center-to-gate distance • Anisotropic low ε_⊥ (4.0 vs 11.7) blocks drain fringing field lines

### 1.1 Dual-Gate Scale Length Derivation
In a double-gate (DG) or gate-all-around (GAA) geometry, the natural electrostatic scale length $\lambda_{DG}$ defines the distance over which the gate electrode electrostatically screens electric field lines originating from the drain:

$$\lambda_{DG} = \sqrt{\frac{\epsilon_{ch}}{2 \epsilon_{ox}} \cdot t_{ch} \cdot t_{ox}}$$

Where $\epsilon_{ch}$ is the channel dielectric permittivity, $\epsilon_{ox}$ is the gate oxide permittivity, $t_{ch}$ is the channel physical thickness, and $t_{ox}$ is the equivalent oxide thickness ($\text{EOT}$).

To prevent destructive short-channel effects—specifically keeping drain-induced barrier lowering ($\text{DIBL} < 50\,\text{mV/V}$) and subthreshold swing ($\text{SS} < 65\,\text{mV/dec}$)—the physical gate length must satisfy:

$$L_g \ge 4.5 \cdot \lambda_{DG}$$

Comparing silicon with monolayer $\text{MoS}_2$ at $\text{EOT} = 0.8\,\text{nm}$:
1. Silicon GAA Nanosheet:
- Minimum allowable thickness before catastrophic mobility collapse: $t_{Si} \approx 3.5\,\text{nm}$.
- Isotropic dielectric permittivity: $\epsilon_{Si} \approx 11.7 \epsilon_0$.
- Scale length:

$$\lambda_{DG,Si} = \sqrt{\frac{11.7}{2 \times 3.9} \times 3.5\,\text{nm} \times 0.8\,\text{nm}} \approx 2.05\,\text{nm}$$
  • Minimum gate length:
$$L_{g,min,Si} \approx 4.5 \times 2.05\,\text{nm} \approx 9.2\,\text{nm}$$

2. Monolayer $\text{MoS}_2$ 2D FET:
- Physical monolayer thickness: $t_{MoS_2} = 0.65\,\text{nm}$.
- Out-of-plane dielectric permittivity: $\epsilon_{\perp,MoS_2} \approx 4.0 \epsilon_0$ (low dielectric constant drastically suppresses capacitive coupling between the drain and the channel).
- Scale length:

$$\lambda_{DG,MoS_2} = \sqrt{\frac{4.0}{2 \times 3.9} \times 0.65\,\text{nm} \times 0.8\,\text{nm}} \approx 0.52\,\text{nm}$$
  • Minimum gate length:
$$L_{g,min,MoS_2} \approx 4.5 \times 0.52\,\text{nm} \approx 2.34\,\text{nm}$$

Monolayer TMDs provide a $4\times$ reduction in natural scale length, establishing 2D semiconductors as the only viable channel material capable of operating below $5\,\text{nm}$ physical gate length.

---

## 2. Contact Physics: Overcoming Fermi Level Pinning

The most critical historical integration barrier for 2D transistors has been high contact resistance ($R_c > 1000\,\Omega\cdot\mu\text{m}$) caused by Fermi level pinning (FLP) at the metal-semiconductor interface.

### 2.1 Metal-Induced Gap States (MIGS) & Schottky Barriers
In classical metal-semiconductor junctions, the termination of the semiconductor wavefunctions into the metal creates Metal-Induced Gap States (MIGS) within the bandgap. The pinning parameter $S$ relates the barrier height $\Phi_B$ to the metal work function $\Phi_M$:

$$\Phi_B = S (\Phi_M - \chi) + (1 - S) \left( \frac{E_g}{q} - \Phi_0 \right)$$

Where $\chi$ is the electron affinity and $\Phi_0$ is the charge neutrality level. When standard metals (e.g., $\text{Au}$, $\text{Ti}$, $\text{Ni}$) are deposited onto $\text{MoS}_2$, high-energy metal atom deposition introduces sulfur vacancies and wave-function hybridization, pinning the Fermi level near the conduction band edge ($S \approx 0.1\text{ to }0.3$) and creating a stubborn Schottky barrier ($\Phi_{SB} \approx 0.2\text{ to }0.4\,\text{eV}$).

### 2.2 Semi-Metallic Contacts (Bismuth and Antimony)
A historic breakthrough pioneered by TSMC and MIT demonstrated that depositing semi-metallic elements—specifically bismuth ($\text{Bi}(0001)$) or antimony ($\text{Sb}(0001)$)—eliminates the Schottky barrier:
1. Vanishing Density of States at the Fermi Level:
- Because semi-metals have zero bandgap but an extremely low density of states at the Fermi energy, the creation of MIGS across the van der Waals interface is virtually eliminated ($S \to 1.0$).
2. Work Function Alignment:
- The Fermi level of $\text{Bi}$ aligns precisely with the conduction band minimum of monolayer $\text{MoS}_2$, yielding $\Phi_{SB} \approx 0\,\text{eV}$.
3. Record Contact Resistance:
- Bismuth contacts achieve an ultralow contact resistance of $R_c \le 123\,\Omega\cdot\mu\text{m}$, approaching the quantum contact resistance limit ($R_Q = h / 2 e^2 M \approx 40\,\Omega\cdot\mu\text{m}$).
- This low resistance enables on-currents exceeding $I_{on} > 1100\,\mu\text{A}/\mu\text{m}$ at $V_{DD} = 0.7\,\text{V}$, rivaling state-of-the-art silicon GAA nanosheets.

---

## 3. High-k Dielectric Integration on Pristine van der Waals Surfaces

Because monolayer TMDs possess no out-of-plane dangling bonds, conventional atomic layer deposition (ALD) precursors (e.g., trimethylaluminum $\text{Al(CH}_3\text{)}_3$ and tetrakis(dimethylamido)hafnium $\text{TDMAH}$) fail to chemisorb onto the inert basal plane, resulting in island agglomeration, pinholes, and gate leakage.

+----------------------------------------------------------------------------------------------------+
|                                    2D DIELECTRIC INTEGRATION METHODS                               |
+----------------------+--------------------+--------------------------------------------------------+
| INTEGRATION TECHNIQUE| APPLIED MATERIALS  | MECHANISM & ADVANTAGES                                 |
+----------------------+--------------------+--------------------------------------------------------+
| 1. Physical Seed     | E-beam Al or Y     | Sub-monolayer (0.5nm) metal deposited and oxidized;    |
|    Layer Oxidation   | -> Al₂O₃ / Y₂O₃    | provides oxygen dangling bonds for subsequent ALD.     |
+----------------------+--------------------+--------------------------------------------------------+
| 2. Low-Damage UV/O₃  | Controlled ozone   | Creates controlled surface oxygen functional groups    |
|    Functionalization | exposure           | without disrupting the underlying in-plane Mo-S bonds. |
+----------------------+--------------------+--------------------------------------------------------+
| 3. van der Waals     | Exfoliated or CVD  | Atomically flat, dangling-bond-free dielectric;        |
|    h-BN Dielectric   | Hexagonal Boron N  | completely eliminates surface charge traps (k ~ 4.0).  |
+----------------------+--------------------+--------------------------------------------------------+

---

## 4. 2D CMOS Roadmap: Complementary nMOS and pMOS Integration

Achieving a practical 2D digital logic platform requires complementary CMOS pairs:

+----------------------------------------------------------------------------------------------------+
|                                2D COMPLEMENTARY LOGIC SPECIFICATIONS                               |
+-----------------------+------------------------------------+---------------------------------------+
| PARAMETER             | nMOS CHANNEL: MoS₂                 | pMOS CHANNEL: WSe₂ / PtSe₂            |
+-----------------------+------------------------------------+---------------------------------------+
| Monolayer Bandgap     | 1.85 eV (Direct)                   | 1.65 eV (Direct)                      |
| Electron Affinity (χ) | 4.2 eV                             | 3.8 eV                                |
| Contact Metal         | Semi-metallic Bismuth (Bi) / Sb    | High work-function Pt / Pd / Ru       |
| Contact Resistance Rc | < 120 Ω·μm                         | < 250 Ω·μm                            |
| Saturation Current Ion| > 1100 μA/μm @ V_DD = 0.7V         | > 650 μA/μm @ V_DD = 0.7V             |
| On/Off Current Ratio  | > 10⁸                              | > 10⁸                                 |
| Target Insertion Node | Foundry A10 / A7 Nodes (Sub-1nm)   | Foundry A10 / A7 Nodes (Sub-1nm)      |
+-----------------------+------------------------------------+---------------------------------------+

Take 2d material transistors further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app