3D NAND String Current Leakage

# 3D NAND String Current Leakage

A 3D NAND string packs dozens to hundreds of memory cells in series along a single vertical channel, and reading any one of them means passing current through every other cell in that same string at once. Every unselected cell along the path has to stay fully conducting — its control gate driven to a pass voltage well above threshold — while only the one selected cell's stored charge actually determines the sensed current. Leakage anywhere in that long series path corrupts the read, which is exactly why string leakage is one of 3D NAND's most consequential and most heavily engineered-around failure mechanisms.

String select transistors at the top and bottom of the string are the specific leakage hot spot, because they're the gatekeepers deciding whether a string participates in a read or write operation at all. The top string select transistor connects the channel to the bit line, and the bottom string select transistor connects it to the common source line; both have to switch cleanly between a hard-off state (isolating unselected strings so their contents don't interfere with the one being accessed) and a hard-on state (letting current flow through the selected string). Gate-induced drain leakage — a high electric field at the gate-drain overlap region causing band-to-band tunneling current even with the transistor nominally off — is the dominant mechanism that corrupts that off-state isolation, and it gets worse as NAND scales to more layers and tighter string-select-transistor dimensions, since both trends push the gate-drain field higher for the same applied voltages.

Leakage in an unselected string shows up as read disturb or a corrupted sense current in the string actually being accessed, since the bit line and common source line are shared resources across many strings at once. If a supposedly off string select transistor leaks enough current, it effectively couples its own string onto the shared bit line or source line during a read that was only meant to sense a completely different string — adding spurious current that skews the sensed value, or over repeated operations, slowly disturbing the stored charge on cells in strings that were never supposed to be touched at all. Because every bit line and source line in a 3D NAND array is shared across the entire block, a single consistently-leaky string select transistor doesn't just degrade its own string's performance — it becomes a noise source for every read that happens to share its bit line.

Process and bias engineering both target this leakage directly, since neither alone fully solves it. Dedicated string-select-transistor process modules — distinct implant and gate-stack recipes from the memory-cell transistors stacked above them — specifically optimize the gate-drain overlap geometry to minimize the field that drives GIDL, at some cost in process complexity relative to building every transistor in the stack identically. On the bias side, careful control of the unselected-string gate voltage during read and program operations — not simply driving it to ground, but to a value chosen specifically to minimize the gate-drain field at the string select transistor — trades a more complex bias scheme for directly suppressed leakage, the same tradeoff logic between process fix and circuit-level mitigation that shows up across most of this walkthrough's reliability material.

Memory redundancy (8134) repairs a defective row or column after the fact, once test has already found it. String leakage control works upstream of that — process and bias engineering aimed at keeping a string select transistor's off-state genuinely off in the first place, so fewer strings ever need repair or get flagged as defective at test to begin with.