advanced packaging substrate
**Advanced Packaging Substrates** are the **organic multilayer circuit boards that mechanically support and electrically connect packaged ICs to printed circuit boards** — serving as the critical intermediate layer between die-level microbump connections (< 50 µm pitch) and PCB-level BGA solder ball connections (> 500 µm pitch), with substrate trace/space dimensions (2–10 µm) and layer count (8–20+ layers) being key determinants of package bandwidth, power delivery quality, and signal integrity.
**Substrate Role in Package Stack**
```
[Die] → C4/µbump (50-100µm pitch) → [Substrate top layer]
[Substrate] multilayer routing (8-20 layers, 2-10µm L/S)
[Substrate bottom] → BGA solder balls (300-1000µm pitch) → [PCB]
```
- Substrate must fan out from die-scale (µm-level) to PCB-scale (mm-level) connections.
- Also: Power delivery (PDN), signal routing, mechanical support, thermal path.
**FC-BGA (Flip-Chip Ball Grid Array)**
- Most common advanced IC package substrate.
- Die flipped → C4 bumps connect to substrate top surface → underfilled with epoxy → BGA balls on bottom.
- Substrate material: ABF (Ajinomoto Build-up Film) as dielectric, copper traces.
- Key specs: 4–16 routing layers, 10–15 µm L/S conventional, down to 2 µm advanced.
**ABF (Ajinomoto Build-up Film)**
- Dominant substrate dielectric material for advanced FC-BGA (AMD, Intel, NVIDIA all use ABF).
- Epoxy-based film, laminated layer by layer → build-up substrate.
- ABF-GX (next-gen): Lower dielectric constant (Dk=3.1), finer pattern capability → 2µm L/S.
- Key vendor: Ajinomoto Fine-Techno (Japan) — near-monopoly → supply chain risk for AI chip demand.
- ABF lead time: 6–12 months → driven chip packaging bottleneck in 2021–2023.
**Substrate Manufacturing Process**
1. Core: Glass-fiber reinforced epoxy (FR4/BT resin) or coreless → laser drill microvias.
2. Build-up: Laminate ABF film → laser drill microvias → electroless + electrolytic Cu plating.
3. Pattern: Photolithography + etch (SAP or mSAP) → form Cu traces.
4. Repeat: 8–20 times → multilayer stack.
5. Surface finish: ENIG (Electroless Ni Immersion Au) → solderability for C4 bumps + BGA balls.
**Semi-Additive Process (SAP) for Fine Lines**
- SAP: Start with thin Cu seed → plate pattern in photoresist openings → strip resist → flash etch seed.
- Achieves 2–5 µm L/S → required for HBM+GPU integrations, < 7nm die packaging.
- mSAP (modified SAP): Industry standard for 8–15 µm L/S → mainstream high-end substrates.
**Coreless Substrates**
- Eliminate thick FR4 core → reduce total package height and warpage.
- Built by building up layers on a sacrificial carrier → remove carrier → thin, flexible substrate.
- Better for ultra-thin packages (smartphones, wearables).
- Mechanical challenge: No core → more warpage during solder reflow → difficult assembly.
**Substrate Suppliers**
| Supplier | Country | Customer |
|----------|---------|----------|
| Ibiden | Japan | Intel, NVIDIA, AMD |
| Shinko Electric | Japan | Intel, AMD |
| Unimicron | Taiwan | Qualcomm, Broadcom |
| AT&S | Austria | Apple, Qualcomm |
| Samsung Electro-Mechanics | Korea | Samsung chips |
**Signal Integrity and PDN on Substrate**
- Controlled impedance routing: 50 Ω single-ended, 100 Ω differential → match transmission line design.
- Decoupling capacitors: Embedded in substrate layers or placed near die → suppress PDN resonance.
- Return path vias: PDN vias accompany signal vias → prevent ground bounce.
- Loss: ABF dielectric loss tangent (Df ≈ 0.01) → for PCIe 5 (32 Gbps) substrates, low-loss ABF variants needed.
Advanced packaging substrates are **the unglamorous but indispensable foundation of every high-performance chip** — as AI accelerators grow to 1000mm² dies requiring 40,000+ C4 bump connections and HBM interfaces with 50µm pitch, substrate technology has moved from commodity to competitive differentiator, with leading substrate manufacturers investing billions in SAP lines capable of 2µm L/S while substrate lead times and ABF supply have become as strategically important as wafer fab capacity in determining AI chip delivery schedules.