analog

**Analog Layout and Matching Techniques** is **the art of physically implementing analog circuits ensuring matched device behavior and minimizing performance degradation from layout-dependent effects — critical for precision analog performance**. Analog layout is fundamentally different from digital layout. Digital layout optimizes for area and routing. Analog layout prioritizes matching, noise isolation, and signal integrity. Matched pairs: differential pairs, current mirrors, and other matched structures are fundamental. Device matching directly impacts precision. Mismatch causes offset, nonlinearity, and gain error. Common-Centroid Layout: matching pairs placed with common centroid — geometric center of positive device coincides with negative device. Minimizes gradient effects (linear spatial variations in temperature, doping, stress). Interdigitation: positive and negative devices interleaved, further improving matching. Dummy devices at edges reduce edge effects. Complete symmetry in layout improves matching. Dummy transistors: non-functional devices placed around active devices to reduce edge effects. Dummy placement with same dummy density outside matched area balances structure. Increases area but improves matching. Orientation matching: all devices oriented identically. Different orientations expose different manufacturing variations. Finger structure: multi-finger transistors improve matching. Single large transistor has more variation than multiple parallel fingers. Parallel fingers with interconnect share variations more uniformly. Substrate noise and coupling: analog blocks sensitive to substrate noise from switching digital. Guard structures isolate analog from digital. Shielded substrate bias reduces coupling. Substrate contacts near sensitive nodes return current locally. Power supply isolation: separate power supplies for analog and digital blocks. Isolated power rails prevent coupling through power supply. Capacitive decoupling near analog loads maintains voltage stability. Clock and reset distribution: keep clocks away from analog regions. Separate clock domain for analog blocks if necessary. Reset signals carefully routed to avoid coupling. High-impedance node protection: sensitive nodes (e.g., op-amp inputs) shielded from adjacent routing. Guard traces at substrate potential surround high-impedance nodes. Minimized routing area near sensitive nodes. Resistor and capacitor matching: passive component matching also important. Thin-film resistors better match than diffusion resistors. Multiple parallel capacitors improve matching. Layout styles for different passives must be consistent. Thermal gradients: local heating affects device matching. Power dissipation distributed evenly. Hot devices moved away from sensitive nodes. Cross-coupled layout: devices that should be at different potentials (inputs to differential pair) placed symmetrically but opposite. Improves common-mode rejection ratio (CMRR). **Analog layout matching through common-centroid placement, interdigitation, and careful shielding ensures device matching critical for precision analog performance and low offset.**