ATPG

**ATPG: Automatic Test Pattern Generation and Fault Coverage** is **computational tools generating test vectors that detect transistor-level faults — efficiently creating comprehensive test suites maximizing fault detection with minimal test vectors**. Automatic Test Pattern Generation (ATPG) automatically generates test vectors targeting specific faults. Instead of manual test development, ATPG systematically identifies and targets faults. Fault Models: Stuck-at faults (node always high or low) are standard. Single stuck-at faults (SSaF) assume one fault at a time. Multiple stuck-at (MSaF) and transition faults are extensions. Gate-level ATPG: targets logic gates and interconnect. Stuck-at-0 or stuck-at-1 at each gate input/output. Transition faults target slow rise/fall times. Bridging faults model unintended connections. ATPG Algorithms: Fault Simulation: simulates circuit with test vectors, determining which faults are detected. Determines fault propagation to observable outputs. Provides coverage feedback. D-algorithm (Roth, 1966): algebraic method tracing logic values through circuit, identifying conflicts and implications. Still foundation of modern ATPG. PODEM (Path-Oriented Decision Making): heuristic search exploring decision tree. Selects inputs minimizing backtracking. FAN (Fanout-free ANalysis): leverages circuit structure (fanout-free regions) for efficiency. Modern tools: employ efficient data structures (BDDs, SAT solvers) enabling handling large circuits. SAT-based ATPG translates problem into satisfiability. SAT solver determines if assignment satisfying formula exists. Highly efficient for large circuits. Fault dominance: if vector detecting fault A also detects fault B, fault B is dominated. ATPG skips dominated faults. Test vector quality: minimize test count while maximizing coverage. Efficient compression reduces test time. Target coverage: typically 95%+ stuck-at coverage. Untargetable faults (redundant logic, inherently unobservable) cannot be detected. Coverage analysis identifies challenging regions. Test time: number of vectors × shift time. Large designs have millions of vectors. Compression and parallelization reduce test time. Defect-Oriented ATPG: targets physical defects (opens, shorts) rather than stuck-at. More realistic but harder to compute. Hybrid approaches combine stuck-at with defect patterns. Transition delay fault ATPG: tests for subtle timing defects. Requires two-pattern testing (setup + clock edge). Overhead is significant but catches speed defects. Timing constraints during test: scan frequency may be limited compared to functional frequency. Test timing violations cause false failures. Careful test pattern design avoids timing issues. In-Circuit Test (ICT): probes interconnect directly, testing connections without logic. Complements ATPG with structural validation. **ATPG efficiently generates test vectors targeting faults, using algorithmic approaches to maximize coverage with minimal test vectors, fundamental to manufacturing test effectiveness.**