bosch process

The Bosch process, specifically designated as time-multiplexed pulsed Deep Reactive Ion Etching (DRIE), is an ultra-high-aspect-ratio anisotropic silicon plasma etching technology that achieves vertical sidewall profiles ($\theta_{\text{sidewall}} = 90.0^\circ \pm 0.3^\circ$) and deep trench features ($D = 50.0\ \mu\text{m}$ to $300.0\ \mu\text{m}$, $AR > 40:1$) by rapidly alternating between conformal fluorocarbon passivation deposition and directional floor-sputter radical etching sub-steps. In advanced ICP DRIE etch tools from Lam Research (Pegasus, Syndion), Applied Materials (Centris Sym3), and Tokyo Electron (Tactras), the Bosch process enables critical silicon micromachining across Through-Silicon Vias (TSVs, $D = 100.0\ \mu\text{m}$, $W = 10.0\ \mu\text{m}$), MEMS inertial sensors (gyroscopes, accelerometers), DRAM deep trench capacitors ($AR > 60:1$), and 3D silicon interposers. The process mechanism operates through two cyclic sub-steps repeated hundreds to thousands of times: (1) a Passivation Phase, in which octafluorocyclobutane ($C_4 F_8$) plasma generates reactive fluorocarbon radicals ($CF_2^\bullet$) that conformally deposit a thin Teflon-like polymer film ($n-(CF_2)_x$, thickness $d_{\text{poly}} = 5.0\text{ nm}$ to $15.0\text{ nm}$) over all exposed surfaces, and (2) an Etch Phase, in which sulfur hexafluoride ($SF_6$) plasma supplies fluorine radicals ($F^\bullet$) and directional positive ions ($SF_x^+, F^+$). RF bias voltage ($V_{\text{bias}} = 150\text{ V}$ to $350\text{ V}$) accelerates ions perpendicular to the wafer, selectively sputtering away the floor polymer film ($t_{\text{clear}} = 0.15\text{ s}$) while leaving sidewall polymer intact. Fluorine radicals spontaneously react with exposed floor silicon to produce volatile $SiF_4 \uparrow$ ($Si + 4F^\bullet \to SiF_4 \uparrow$), achieving instantaneous silicon etch rates up to $25.0\ \mu\text{m/min}$ while maintaining high selectivity to underlying silicon dioxide or photoresist masks ($S_{\text{Si:mask}} > 200:1$). Managed across leading-edge fabs including TSMC, Intel, Samsung, SK hynix, Micron, and IBM using TCAD profile simulation from Synopsys (Sentaurus Etch) and Coventor (SEMulator3D), unmitigated Bosch DRIE causes sidewall scalloping defects ($h_{\text{scallop}} = 50.0\text{ nm}$ to $150.0\text{ nm}$), aspect-ratio-dependent etch lag, profile bowing, and notch formation at dielectric etch stop interfaces. Bosch Process: Time-Multiplexed DRIE Kinetics Alternating C4F8 Passivation & SF6 Directional Floor Sputter / Isotropic Etch 1. Passivation Step (C4F8 Plasma) CF2 Radical Deposition Conformal Polymer Film d_poly = 8.0 nm Passivation Time t_pass = 1.0 s 2. Etch Step (SF6 Plasma) Directional Ion Sputter + F* Etch Floor Clear t_clear = 0.15 s | Scallop h = 25 nm ```flowchart Passivation Step (C4F8 Plasma, 1.0 s) → CF2 Polymerization → Conformal Teflon-Like Film Deposition (d_poly = 8.0 nm) → Fast Gas Valve Switch (t_switch < 50 ms) → Etch Step (SF6 Plasma, 1.5 s) → Directional SFx+ Ion Acceleration → Floor Polymer Sputter Clearance (t_clear = 0.15 s) → Fluorine Radical Isotropic Silicon Etch (Si + 4F* → SiF4) → Sidewall Scallop Formation (h_scallop = 25 nm) → Parameter Ramping APC → High Aspect Ratio Vertical Trench (AR > 40:1) ``` **Conformal fluorocarbon polymer deposition kinetics govern sidewall protection in the Bosch process.** In the passivation sub-step, octafluorocyclobutane ($C_4 F_8$) gas is ionized in a high-density Inductively Coupled Plasma (ICP, source power $W_{\text{ICP}} = 2500\text{ W}$, pressure $P = 25\text{ mTorr}$). Electron-impact dissociation breaks $C_4 F_8$ into $CF_2^\bullet$ radicals ($C_4 F_8 + e^- \to 4 CF_2^\bullet + e^-$), which adsorb onto all exposed wafer surfaces with a sticking probability $\gamma_{\text{stick}} = 0.12$. Polymer growth rate $R_{\text{poly}}$ scales directly with radical concentration $C_{CF_2}$: $$R_{\text{poly}} = \frac{1}{\rho_{\text{poly}}} s_0 C_{CF_2} \bar{v}_{\text{thermal}}$$ Where $\rho_{\text{poly}} = 2.15\text{ g/cm}^3$ is the density of the fluorocarbon polymer film, and $s_0 = 0.10$ is the initial sticking coefficient. During a typical passivation step duration ($t_{\text{pass}} = 1.0\text{ s}$), a conformal polymer film of thickness $d_{\text{poly}} = 8.0\text{ nm}$ is deposited uniformly across both horizontal feature floors and vertical sidewalls. **Directional ion sputtering clears floor polymer to initiate isotropic fluorine radical silicon etching.** When the chamber gas supply switches to $SF_6$ ($t_{\text{switch}} < 50\text{ ms}$), RF bias power ($W_{\text{bias}} = 120\text{ W}$, $V_{\text{bias}} = 220\text{ V}$) accelerates directional $SF_x^+$ and $F^+$ ions normal to the wafer surface. Directional ion flux $J_{\text{ion}}$ preferentially sputters away the fluorocarbon polymer at the trench floor ($\theta = 0^\circ$). The polymer clearance time $t_{\text{clear}}$ is: $$t_{\text{clear}} = \frac{d_{\text{poly}} \cdot \rho_{\text{poly}}}{Y_{\text{sputter}} \cdot J_{\text{ion}} \cdot m_{\text{monomer}}}$$ For $d_{\text{poly}} = 8.0\text{ nm}$ and ion sputtering yield $Y_{\text{sputter}} = 1.8\text{ monomer/ion}$, clearance occurs in $t_{\text{clear}} = 0.15\text{ s}$. Once floor silicon is exposed, fluorine radicals ($F^\bullet$) spontaneously react with silicon to form volatile $SiF_4 \uparrow$ ($Si + 4F^\bullet \to SiF_4 \uparrow$). Because sidewalls ($\theta = 90^\circ$) experience zero normal ion flux ($J_{\text{ion,side}} \approx 0$), the sidewall polymer film remains intact, preventing lateral chemical etching. **Periodic chemical etch sub-steps create sidewall scallop undulations.** The isotropic chemical etch phase of exposed floor silicon continues for the remainder of the etch step duration ($t_{\text{etch}} - t_{\text{clear}} = 1.35\text{ s}$). Isotropic radical etching expands outward in a hemispherical wave, creating a characteristic crest-and-trough sidewall pattern called a **scallop**. Scallop height $h_{\text{scallop}}$ and cycle depth $\Delta D_{\text{cycle}}$ are expressed as: $$h_{\text{scallop}} \approx ER_{\text{iso}} \cdot (t_{\text{etch}} - t_{\text{clear}})$$ $$\Delta D_{\text{cycle}} = ER_{\text{vert}} \cdot (t_{\text{etch}} - t_{\text{clear}})$$ For an isotropic etch rate $ER_{\text{iso}} = 1.10\ \mu\text{m/min} = 18.3\text{ nm/s}$, scallop height per cycle is $h_{\text{scallop}} = 18.3\text{ nm/s} \times 1.35\text{ s} = 24.7\text{ nm}$. Scallop pitch $\lambda_{\text{scallop}}$ equals the vertical silicon depth etched per cycle ($\Delta D_{\text{cycle}} = 320.0\text{ nm}$). Fast gas switching valves ($t_{\text{step}} = 0.4\text{ s}$) reduce scallop height to $h_{\text{scallop}} < 8.0\text{ nm}$ for smooth Through-Silicon Via (TSV) liners. **Parameter ramping algorithms dynamically adjust etch step durations to offset Knudsen diffusion limitations in deep trenches.** As trench depth increases from $D = 10.0\ \mu\text{m}$ to $D = 150.0\ \mu\text{m}$, Knudsen transport limitations reduce radical supply to the feature floor (RIE lag). Advanced process control (APC) counters RIE lag by dynamically ramping SF6 etch step duration ($t_{\text{etch}} = 1.5\text{ s} \to 3.2\text{ s}$) and ICP source power ($W_{\text{ICP}} = 2500\text{ W} \to 4200\text{ W}$) linearly with cycle count $N$, maintaining constant net etch rate ($7.5\ \mu\text{m/min}$) across the entire trench depth. **High chemical selectivity to the etching mask enables extreme depth aspect ratios while maintaining top critical dimensions.** Silicon-to-oxide selectivity $S_{\text{Si:SiO2}} = ER_{\text{Si}} / ER_{\text{SiO2}} = 210:1$ allows a thin $1.0\ \mu\text{m}$ oxide hard mask to withstand $500\text{ etch cycles}$ down to $D = 150.0\ \mu\text{m}$. Sidewall polymer passivation prevents lateral mask undercut, preserving top feature opening width ($W_{\text{top}} = 10.0\ \mu\text{m} \pm 0.15\ \mu\text{m}$) throughout the process. | DRIE Process Regime | Passivation t_pass (s) | Etch t_etch (s) | C4F8 Flow (sccm) | SF6 Flow (sccm) | Scallop Height h (nm) | Net ER (µm/min) | Selectivity Si:SiO2 | |---|---|---|---|---|---|---|---| | High-Speed TSV (W = 10 µm) | 1.2 s | 2.0 s | 180 sccm | 450 sccm | 85.0 nm | 14.5 µm/min | 180:1 | | Ultra-Smooth TSV (W = 5 µm) | 0.4 s | 0.5 s | 120 sccm | 280 sccm | 6.5 nm | 4.2 µm/min | 140:1 | | Deep MEMS Sensor (W = 25 µm)| 1.8 s | 3.0 s | 220 sccm | 600 sccm | 140.0 nm | 18.2 µm/min | 240:1 | | DRAM Deep Trench (W = 0.1 µm)| 0.8 s | 1.2 s | 90 sccm | 180 sccm | 12.0 nm | 3.5 µm/min | 110:1 | | 3D NAND Channel (W = 0.08 µm)| 0.6 s | 0.8 s | 75 sccm | 150 sccm | 8.0 nm | 2.8 µm/min | 95:1 | | Cryo-Bosch Hybrid (-40°C) | 0.5 s | 0.8 s | 60 sccm | 200 sccm | 4.2 nm | 5.8 µm/min | 210:1 | Read the Bosch Process through a *time-multiplexed polymer passivation and floor-sputter directional etching* lens rather than a *simple continuous etch* lens. In 3D semiconductor manufacturing, the Bosch process is not a static two-step recipe; it is a highly dynamic kinetic equilibrium between fluorocarbon radical surface polymerization, directional ion sputtering, and chemical radical transport. Every parameter in modern DRIE tools — from piezoelectric gas valve switching speeds and dual-frequency RF bias generators to parameter ramping APC algorithms and turbomolecular pumping speeds — represents the active tuning of cyclical surface reactions. Master these surface polymerization kinetics and time-multiplexed switching dynamics, and your process integration architectures will consistently achieve ultra-high-aspect-ratio vertical trench profiles across sub-2nm GAA NanoSheet contacts, MEMS sensors, and 3D Through-Silicon Vias (TSVs). --- ## Passivation Polymer Film Deposition Kinetics Conformal fluorocarbon polymer film ($n-(CF_2)_x$, $d_{\text{poly}} = 8.0\text{ nm}$) deposition during $C_4F_8$ plasma sub-step ($t_{\text{pass}} = 1.0\text{ s}$). Passivation Polymer Film Deposition Kinetics C4F8 radical polymerization vs conformal Teflon-like film thickness d_poly Conformal Fluorocarbon Polymer (n-(CF2)x) • C4F8 Plasma Dissociation: C4F8 + e⁻ → 4 CF2* + e⁻ (Radical density n_CF2 = 3.5 × 10¹4 /cm³) • Polymer Growth Rate: R_poly = (1 / ρ_poly) · s0 · C_CF2 · v_thermal = 8.0 nm/s at W_ICP = 2500 W • Conformal Coverage: Sticking coefficient s0 = 0.10 ensures uniform sidewall & floor thickness • Step Time Control: t_pass = 1.0 s deposits exactly d_poly = 8.0 nm protective Teflon film Fluorocarbon radical polymerization ($C_4F_8 \to 4 CF_2^\bullet$) forms $d_{\text{poly}} = 8.0\text{ nm}$ conformal Teflon film in $t_{\text{pass}} = 1.0\text{ s}$. During the passivation step, $C_4 F_8$ gas flows into the ICP source chamber at $180\text{ sccm}$. High ICP source power ($W_{\text{ICP}} = 2500\text{ W}$) dissociates $C_4 F_8$ into $CF_2^\bullet$ radicals. Polymerization occurs on exposed silicon surfaces according to surface radical flux $J_{CF_2} = \frac{1}{4} C_{CF_2} \bar{v}_{\text{thermal}}$. The resulting Teflon-like polymer film ($n-(CF_2)_x$) exhibits high chemical resistance against isotropic fluorine radical attack. Conformal step coverage $\theta_{\text{coverage}} = d_{\text{side}} / d_{\text{top}} > 0.92$ is maintained by optimizing chamber pressure ($P = 25\text{ mTorr}$) to ensure radical mean free path $\lambda_{\text{mfp}}$ exceeds trench opening width. --- ## Anisotropic Directional Ion Floor Polymer Clearing & Isotropic Etch Directional ion sputtering ($V_{\text{bias}} = 220\text{ V}$, $t_{\text{clear}} = 0.15\text{ s}$) clears floor polymer, allowing $F^\bullet$ radicals to etch silicon ($Si + 4F^\bullet \to SiF_4 \uparrow$). Anisotropic Floor Clearing & Isotropic Silicon Etch Directional ion floor polymer sputter vs F* radical chemical silicon etching • Floor Clearance Time: t_clear = (d_poly · ρ_poly) / (Y_sputter · J_ion · m_monomer) = 0.15 s • Directional Ion Sputtering: V_bias = 220 V accelerates SFx⁺ ions normal to floor (θ = 0°) • Sidewall Protection: Parallel sidewalls (θ = 90°) experience zero ion impact, retaining polymer • Volatile Reaction: Si + 4 F* → SiF4 ↑ (Instantaneous silicon etch rate ER_vert = 18.2 µm/min) RF bias voltage ($V_{\text{bias}} = 220\text{ V}$) drives directional ion floor sputtering ($t_{\text{clear}} = 0.15\text{ s}$), exposing silicon to $F^\bullet$ radicals. In the etch phase, $SF_6$ gas is introduced at $450\text{ sccm}$. ICP source power ($W_{\text{ICP}} = 2800\text{ W}$) generates high fluorine radical density ($n_F = 1.2 \times 10^{15}\text{ cm}^{-3}$). Applied RF bias voltage ($V_{\text{bias}} = 220\text{ V}$) creates a directional ion sheath. Positive ions ($SF_5^+, F^+$) strike horizontal surfaces with normal energy $E_{\text{ion}} = 220\text{ eV}$, sputtering the floor polymer film in $t_{\text{clear}} = 0.15\text{ s}$. Exposed floor silicon undergoes rapid chemical etching by $F^\bullet$ radicals ($Si + 4F^\bullet \to SiF_4 \uparrow$). Sidewalls remain protected by intact fluorocarbon polymer because ion trajectories are strictly parallel to vertical sidewalls. --- ## Sidewall Scallop Height & Pitch Formation Mechanics Isotropic radical etching during $(t_{\text{etch}} - t_{\text{clear}})$ creates periodic sidewall scallops ($h_{\text{scallop}} = 24.7\text{ nm}$, pitch $\lambda_{\text{scallop}} = 320.0\text{ nm}$). Sidewall Scallop Formation & Pitch Kinetics Isotropic chemical undercut h_scallop vs cycle period T_cycle h = 24.7 nm λ = 320 nm • Scallop Height Formula: h_scallop = ER_iso · (t_etch - t_clear) = 18.3 nm/s × 1.35 s = 24.7 nm • Cycle Depth Pitch: λ_scallop = ER_vert · (t_etch - t_clear) = 320.0 nm per cycle • Fast Switching Reduction: Reducing t_step to 0.4 s shrinks scallop height h_scallop < 8.0 nm • TSV Liner Integrity: Smooth sidewalls (h < 10 nm) prevent physical vapor deposition dielectric voids Scallop height $h_{\text{scallop}} = 24.7\text{ nm}$ scales directly with isotropic etch time $(t_{\text{etch}} - t_{\text{clear}})$. Repeated cycling creates periodic wave-like undulations along trench sidewalls. Each cycle leaves a scallop peak where the protective polymer terminated and a scallop trough where isotropic radical etching expanded laterally. Scallop peak-to-valley height $h_{\text{scallop}}$ determines sidewall roughness. In 3D packaging TSVs, excessive scallop roughness ($h_{\text{scallop}} > 50.0\text{ nm}$) causes void formation during subsequent $SiO_2$ barrier and $Cu$ seed physical vapor deposition (PVD). Reducing step time via fast switching valves ($t_{\text{step}} = 0.4\text{ s}$) produces smooth sidewalls ($h_{\text{scallop}} < 8.0\text{ nm}$), ensuring void-free metalization. --- ## Parameter Ramping APC and Fast Switching Valves Parameter ramping APC increases $t_{\text{etch}}$ ($1.5\text{ s} \to 3.2\text{ s}$) and $W_{\text{ICP}}$ ($2500\text{ W} \to 4200\text{ W}$) to eliminate RIE lag in deep trenches ($D > 100\ \mu\text{m}$). Parameter Ramping APC & Fast Gas Switching Dynamic t_etch and ICP source power scaling vs trench aspect ratio Ramped Power: W_ICP (2500 W → 4200 W) Ramped Etch Time: t_etch (1.5 s → 3.2 s) • RIE Lag Compensation: Radical flux depletion at depth D > 100 µm compensated by linear APC ramping • Fast Valve Response: Piezoelectric fast gas valves achieve t_switch < 50 ms between C4F8 & SF6 • Constant Etch Rate: Holds net silicon etch rate fixed at ER_net = 7.5 ± 0.2 µm/min across all depths • Vertical Sidewall Control: Maintains taper angle θ_taper = 90.0° ± 0.3° down to AR 40:1 Dynamic parameter ramping APC maintains constant net etch rate ($7.5\ \mu\text{m/min}$) down to $D = 150.0\ \mu\text{m}$. As the trench etches deeper into the silicon substrate, Knudsen diffusion conductance losses reduce fluorine radical transport to the feature floor (RIE lag). Without intervention, net etch rate drops by $> 60\%$. Advanced Process Control (APC) implements linear parameter ramping algorithms: $$t_{\text{etch}}(N) = t_{\text{etch,0}} + \alpha_{\text{ramp}} \cdot N$$ $$W_{\text{ICP}}(N) = W_{\text{ICP,0}} + \beta_{\text{ramp}} \cdot N$$ Where $N$ is cycle count, $\alpha_{\text{ramp}} = 0.0034\text{ s/cycle}$, and $\beta_{\text{ramp}} = 3.4\text{ W/cycle}$. Dynamic ramping offsets radical transport bottlenecks, ensuring identical etch depth increment $\Delta D_{\text{cycle}} = 320.0\text{ nm}$ per cycle throughout a $500\text{-cycle}$ process. --- ## Silicon-to-Mask Selectivity and High-Aspect-Ratio TSV Profiles High silicon-to-mask selectivity ($S_{\text{Si:SiO2}} > 200:1$) enables deep TSVs ($AR > 40:1$, depth $D = 150.0\ \mu\text{m}$). Silicon-to-Mask Selectivity & HAR TSV Profiles Oxide hard mask erosion rate vs high-aspect-ratio TSV profile fidelity Deep TSV (D = 150 µm, W = 10 µm) Aspect Ratio AR = 15:1 to 40:1 • Silicon-to-Oxide Selectivity: S_Si:SiO2 = ER_Si / ER_SiO2 = 210:1 (Oxide mask erosion < 750 nm) • Photoresist Selectivity: S_Si:PR = 75:1 to 110:1 (Allows direct photoresist mask etching) • Profile Taper Control: Precise balance of t_pass / t_etch maintains 90.0° ± 0.3° vertical sidewalls • Notch Suppression: Pulsed bias at dielectric etch-stop interface eliminates bottom notch defects Silicon-to-oxide selectivity $S_{\text{Si:SiO2}} = 210:1$ restricts hard mask erosion to $< 750\text{ nm}$ over $150.0\ \mu\text{m}$ deep TSV etches. High chemical selectivity to the etching mask is essential for deep DRIE. Thermal $SiO_2$ or PECVD oxide hard masks resist fluorine radical attack because silicon-oxygen bonds ($E_{\text{bond}} = 8.2\text{ eV}$) require directional ion energy to break. Fluorocarbon polymer deposition during the passivation phase further shields the oxide mask. Overall selectivity $S_{\text{Si:SiO2}} = ER_{\text{Si}} / ER_{\text{SiO2}} = 210:1$ allows a thin $1.0\ \mu\text{m}$ oxide mask to pattern a $150.0\ \mu\text{m}$ deep silicon TSV trench. At the underlying dielectric etch-stop interface ($SiO_2$ or $Si_N_4$), switching to low-frequency pulsed bias ($f_{\text{bias}} = 100\text{ Hz}$) prevents charging-induced ion deflection and eliminates floor notch formation. --- ## Metrology Qualification: HR-STEM and Inline 3D OCD Scallop Audit Inline Mueller matrix 3D OCD scatterometry and cross-sectional HR-STEM qualify Bosch DRIE scallop height $h_{\text{scallop}}$ and trench depth $D$. Inline 3D OCD & HR-STEM DRIE Qualification Mueller matrix spectroscopic ellipsometry & high-resolution cross-sectional TEM audit 1. Inline 3D OCD Metrology • Spectroscopic Ellipsometry • Measures depth D & taper θ • Non-destructive 100% audit Precision: σ < 0.25 nm High Throughput (110 wph) 2. Cross-Section HR-STEM • High-resolution TEM imaging • Direct h_scallop & pitch audit • Calibrates OCD RCWA models Resolution: 0.1 nm Golden Calibration Gate 3. Closed-Loop APC Control • Real-time parameter ramping • Adjusts t_pass & t_etch • Holds θ_taper = 90.0° ± 0.3° Run-to-run APC control Yield Gate > 99.8% Bosch Process Fab Qualification Criteria 1. Sidewall Scallop Limit: h_scallop < 10.0 nm for ultra-smooth TSVs, < 30.0 nm for MEMS sensors. 2. Profile Taper Budget: Sidewall angle θ_taper = 90.0° ± 0.3° across full trench depth D = 150 µm. 3. Mask Selectivity Budget: Remaining oxide hard mask thickness > 250 nm after complete TSV clearing. 4. Fab Execution: Verified across TSMC, Intel, Samsung, SK hynix, Micron, IBM using Synopsys & Coventor TCAD. Inline Mueller matrix 3D Optical Critical Dimension (OCD) scatterometry and HR-STEM cross-sections verify Bosch DRIE profile fidelity ($\theta_{\text{taper}} = 90.0^\circ \pm 0.3^\circ$) across TSMC, Intel, Samsung, SK hynix, Micron, and IBM production wafers, modeled in Synopsys Sentaurus and Coventor SEMulator3D. Inline Mueller matrix Optical Critical Dimension (OCD) scatterometry extracts deep trench profiles by measuring multi-wavelength spectroscopic polarization signatures across periodic target arrays. Raw ellipsometric parameters ($\Psi, \Delta$) are reconstructed using rigorous coupled-wave analysis (RCWA) parameterized by a multi-segment profile vector: $$\mathbf{p} = \left[ W_{\text{top}}, W_{\text{mid}}, W_{\text{bottom}}, D_{\text{trench}}, h_{\text{scallop}}, \theta_{\text{taper}}, d_{\text{mask}} \right]$$ Extracted depth profiles achieve non-destructive precision $\sigma < 0.25\text{ nm}$ at throughputs exceeding $110\text{ wafers/hour}$. Output metrology data feeds directly into run-to-run Advanced Process Control (APC) models on Lam Research Pegasus, Applied Materials Centris Sym3, and Tokyo Electron Tactras etchers, automatically updating parameter ramping slopes ($\alpha_{\text{ramp}}, \beta_{\text{ramp}}$) to hold scallop height $h_{\text{scallop}} < 10.0\text{ nm}$ and guarantee $> 99.8\%$ functional TSV yield in 3D advanced packaging architectures.

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