burn-in test

Burn-in test is a high-temperature, elevated-voltage stress test applied to packaged ICs to accelerate and screen out infant mortality failures before shipping to customers. Test conditions: (1) Temperature—125°C junction temperature typical (some applications 150°C); (2) Voltage—10-20% above nominal VDD to accelerate failure mechanisms; (3) Duration—24-168 hours depending on product and reliability requirements; (4) Exercising—dynamic patterns toggle logic to activate latent defects. Burn-in types: (1) Static burn-in—apply voltage and temperature only (simpler, lower cost); (2) Dynamic burn-in—apply functional patterns during stress (more effective at finding defects); (3) IDDQ burn-in—monitor quiescent current during burn-in for enhanced detection; (4) Monitored burn-in—test during burn-in (detect failures in real-time). Equipment: (1) Burn-in oven—temperature-controlled chamber holding burn-in boards; (2) Burn-in boards—PCBs with sockets for 32-512+ devices, provide power and signals; (3) Driver electronics—pattern generators and power supplies; (4) Environmental control—temperature uniformity ±3°C across oven. Defects screened: (1) Gate oxide weak spots (TDDB precursors); (2) Latent metal voids (EM, stress migration); (3) Contamination-induced leakage paths; (4) Marginal contacts/vias; (5) ESD damage from handling. Economics: burn-in adds $0.50-$5.00+ per device (board depreciation, oven time, electricity, handling)—significant cost factor. Industry trends: (1) Reduced burn-in—better processes enable shorter or eliminated burn-in for consumer; (2) Voltage stress at final test—substitute for time-based burn-in; (3) WLBI (wafer-level burn-in)—stress before packaging saves packaging cost on failures; (4) Statistical burn-in—test sample lots rather than 100%. Automotive and military continue requiring extensive burn-in for zero-DPPM targets and high-reliability applications.