chip

Making a modern chip means building a three-dimensional structure of 60–100+ patterned layers onto a silicon wafer, one atomic-scale layer at a time. At a high level, the flow looks like this:\n\n```flowchart\n{\n "rows": [\n { "type": "nodes", "items": [\n { "title": "Design and tape-out", "sub": "RTL to GDSII layout", "tone": "neutral" },\n { "title": "Wafer preparation", "sub": "Ingot growth, slicing", "tone": "neutral" }\n ]},\n { "type": "arrow" },\n { "type": "group", "title": "Front-end fab loop", "note": "Repeated 60 to 100+ layers", "cycle": true, "items": [\n { "title": "Deposition", "sub": "CVD, ALD thin films", "tone": "green" },\n { "title": "Lithography", "sub": "EUV pattern exposure", "tone": "green" },\n { "title": "Etch", "sub": "Plasma pattern transfer", "tone": "green" },\n { "title": "Doping and anneal", "sub": "Ion implantation", "tone": "green" }\n ], "loop": "↻ next layer" },\n { "type": "arrow" },\n { "type": "nodes", "items": [\n { "title": "Metallization and test", "sub": "Copper wiring, wafer probe", "tone": "orange" },\n { "title": "Dicing and packaging", "sub": "Chiplets, HBM, CoWoS", "tone": "orange" }\n ]}\n ]\n}\n```\n\nA few things are worth knowing about why this process is so remarkable, especially for AI and GPU hardware:\n\n**The layer count is the real story.** A leading-edge logic chip isn't a flat pattern — it's a 3-D stack built over 60–100+ mask layers. The transistors themselves (front-end-of-line) occupy only the bottom sliver; everything above is 10–15 levels of copper interconnect wiring them together. Each layer needs its own deposition–litho–etch cycle, which is why a wafer takes roughly 3–4 months to move through a fab and touches hundreds of process steps. One defect at any step can kill a die, so yield compounds multiplicatively — the economics of chipmaking are essentially a fight against that exponential.\n\n```svg\n\n```\n\n**Lithography is the bottleneck and the marvel.** EUV scanners use 13.5 nm light generated by hitting molten-tin droplets with a laser about 50,000 times per second, then steer it with mirrors polished to sub-atomic flatness (no lens can refract EUV — everything is reflective, in vacuum). Each machine costs more than 200 million dollars (High-NA versions run closer to 400 million), and ASML is the only company on Earth that builds them. Because the printed features are far smaller than the wavelength, it takes enormous computational lithography — including GPU-accelerated inverse lithography, which NVIDIA's cuLitho targets — to pre-distort mask patterns so they print correctly.\n\n**Doping is what makes silicon a semiconductor at all.** Pure silicon barely conducts; implanting boron or phosphorus ions at precise depths and concentrations creates the p–n junctions that let transistors switch. Modern gate-all-around transistors demand atomic-layer-level control at this stage.\n\n**Packaging has become the new frontier.** With transistor scaling slowing, more of the performance gain now comes from advanced packaging: TSMC's CoWoS places GPU dies and HBM stacks on a silicon interposer, and chiplet architectures (AMD's MI300, for example) stitch multiple dies together. CoWoS capacity — not wafer capacity — has repeatedly been the binding constraint on AI-GPU supply.\n\n**The industry structure mirrors the process.** Fabless designers (NVIDIA, AMD, Apple) hand GDSII files to foundries (TSMC, Samsung, Intel Foundry), who depend on a tiny set of equipment makers (ASML, Applied Materials, Lam Research, KLA, Tokyo Electron) and ultra-pure materials suppliers — one of the deepest and most geopolitically sensitive supply chains in existence.\n\nRead a chip through a *yield-times-layers* lens rather than a *transistor-count* lens: the number that decides whether a design is manufacturable and profitable is how many of the 60–100+ patterned layers survive defect-free, compounded across hundreds of steps — not the headline gate length. Every hard problem in this flow — EUV cost, computational lithography, atomic-scale doping, CoWoS packaging — is ultimately a different way of protecting that compounding yield.\n