chip floorplan

**Chip Floorplanning** is the **high-level placement of major functional blocks (CPU core, cache, memory controller, I/O, analog blocks) and I/O pads — determining overall chip size, aspect ratio, and supply/signal distribution strategy — enabling cost-effective die design and guiding detailed implementation**. Floorplanning is the first physical design step. **Block and I/O Placement** Floorplan defines: (1) location of major blocks (x, y coordinates), (2) I/O pad locations (arranged around die perimeter), (3) power distribution (pad placement relative to supply-hungry blocks). Block locations are determined by: (1) size and shape (blocks have intrinsic aspect ratio constraints), (2) connectivity (related blocks placed close), (3) thermal management (hot blocks distributed, not clustered). I/O placement follows I/O protocol: (1) sequential I/O (memory bus) grouped together, (2) power/ground pads distributed (uniform supply), (3) high-speed I/O (differential pairs, clock inputs) placed for signal integrity. **Aspect Ratio Selection** Chip aspect ratio (width / height) affects routing congestion and thermal distribution. Square chips (aspect ratio ~1:1) are preferred for: (1) balanced routing channel size, (2) uniform thermal distribution. Rectangular chips (aspect ratio >2:1) are used when: (1) I/O density is high on one edge (e.g., memory bus), (2) thermal hotspots must be spread (elongate chip), (3) cost pressure (wider chips may have lower defect rate per unit area). Typical aspect ratio range is 0.8-1.5 (nearly square). **Power Domain Allocation** Floorplan allocates space for: (1) supply pads (C4 bumps or BGA balls), (2) power straps (main distribution), (3) decap cells (on-chip capacitors for droop reduction). Power-hungry blocks (processor core, memory controllers) are placed near pads (short current path reduces IR drop). Low-power blocks (analog, I/O) are placed farther from pads (acceptable higher drop). Separate power domains (e.g., core domain, I/O domain) are assigned separate pad and strap regions for independent power management. **Channel Routing Area Estimation** Between blocks, routing space must be reserved for signal interconnects (metal tracks). Channel height is estimated based on: (1) number of nets crossing channel (via fanout, signal count), (2) track pitch (determined by technology, typically 0.5-2 µm for advanced nodes), (3) strap routing (power/ground nets consume tracks). For example, 1000 nets crossing channel, 0.1 µm pitch, 50 µm channel height accommodates 500 tracks (sufficient). Undersized channels cause congestion (rerouting required, delays increased). **Bump/Pad Placement Co-optimization** Pad placement is co-optimized with floorplan: (1) power pads placed near high-current blocks, (2) signal pads arranged for I/O protocol/interface, (3) ground pads interspersed (return path), (4) spacing uniform (avoid local inductance). Bump assignment (assigning nets to pads) is often done after floorplan but influenced by floorplan (power pads must reach power straps, clock pad must reach CTS root). Co-optimization improves power integrity and signal integrity. **Partition Timing-Driven Floorplanning** Blocks are placed to minimize interconnect delay: (1) critical-path blocks placed close (e.g., CPU core and L1 cache adjacent), (2) non-critical blocks placed farther (longer interconnect acceptable). Timing-driven floorplanning uses estimated interconnect delay (wire delay between blocks) and compares to timing budget. Iterative refinement: if timing critical, blocks are moved closer. **Macro Placement (SRAM, PHY)** Embedded memory (SRAM) and I/O PHY are rigid blocks (hard macros) with fixed size/shape. Macro placement is critical: (1) SRAM placement affects timing (distance to processor core), (2) PHY placement affects I/O signal integrity (distance to pads), (3) spacing around macros must accommodate power/ground routing. Macro placement is often done manually or semi-automated (fixed, not moved during detailed placement). **Hierarchy-Aware Floorplanning** Designs are hierarchical (cores, blocks, subblocks). Floorplan respects hierarchy: (1) subblock placement within assigned block region, (2) power distribution matches hierarchy (primary straps at top level, secondary within block), (3) routing follows hierarchy (inter-block nets routed at top level, intra-block at block level). Hierarchy enables modular design and parallel implementation (different teams work on different blocks). **DEF/LEF-Based Flow** Physical design uses two key file formats: (1) LEF (Library Exchange Format) — describes block/macro boundaries, pins, blockages (internal routing), (2) DEF (Design Exchange Format) — describes floorplan (block placement, I/O pad placement, routing). Floorplan is defined in DEF: COMPONENTS section lists block placements, PINS section lists I/O. Detailed tools (Innovus, ICC2) import DEF floorplan and perform placement/routing within DEF constraints. **Floorplan Validation** Floorplan is validated for: (1) routing feasibility (sufficient channel space, no congestion), (2) timing feasibility (estimated delay on critical paths meets budget), (3) power integrity (IR drop map estimated, acceptable). Validation often requires quick turnaround (minutes, not hours). Floorplan optimization tools (Innovus, ICC2) provide automated estimation and optimization. **Summary** Chip floorplanning is a strategic design step, balancing performance, power, cost, and manufacturability. Continued advances in automated floorplanning and timing-driven optimization drive improved design quality and convergence. --- **Physical Design Flow — From RTL to GDSII.** The physical design flow transforms a verified register-transfer level (RTL) description into a manufacturing-ready GDSII file through a sequence of increasingly constrained optimization steps. Each step must satisfy design rules, timing constraints, and power/thermal limits simultaneously — and the flow iterates 20–50 times before all constraints converge (timing closure). **Chip Floorplanning — Partitioning for Power and Performance.** Floorplanning divides the die into regions (blocks, macros, I/O rings, power domains) and determines their relative positions before detailed placement begins. A good floorplan minimizes total wirelength (reducing delay and power), places high-bandwidth blocks adjacent to memory interfaces, separates noisy digital from sensitive analog, and distributes power grid connections to avoid IR-drop hotspots. At the 2 nm node a 200 mm$^2$ SoC contains 50–200 hard macros (SRAM, PLL, SerDes PHY, HBM PHY) that must be placed first as fixed obstacles, then 500M+ standard cells fill the remaining area at 2,000+ cells/$\mu$m$^2$. **IR Drop and Power Integrity.** Supply voltage at the transistor ($V_\text{dd,local}$) is always less than the package supply ($V_\text{dd,pkg}$) due to resistive drop through the power distribution network: $\Delta V = I \times R_\text{PDN}$. At $V_\text{dd} = 0.7$ V, a 5% IR-drop budget allows only 35 mV — meaning the total PDN resistance from package bump to transistor must stay below $35 \text{ mV} / 100 \text{ A} = 0.35$ m$\Omega$ for a 100A power domain. This requires: wide power stripes on upper metals (10–20 $\mu$m), dense via arrays, and decoupling capacitance (100–200 nF/mm$^2$) to handle switching transients. Dynamic IR-drop (during clock edges when millions of cells switch simultaneously) can exceed static drop by 3–5$\times$, requiring time-domain power integrity simulation (Synopsys RedHawk, Cadence Voltus) at the signoff stage. **Signal Integrity — Crosstalk and Noise.** At 22 nm M1 pitch, adjacent wires are separated by only 11 nm of low-$k$ dielectric — the coupling capacitance between neighbors approaches 50% of total wire capacitance. When an aggressor wire switches while a victim wire is quiet, the coupling injects a noise pulse ($\Delta V = C_c / (C_c + C_g) \times V_\text{swing}$) that can reach 30–50% of $V_\text{dd}$. Crosstalk also causes timing violations: a victim transitioning in the same direction as the aggressor speeds up (reduces delay), while opposite-direction switching slows down (increases delay) — creating $\pm$20–50 ps timing variation that must be accounted for in STA (static timing analysis). Shielding critical nets with grounded wires, spacing rules, and routing track assignment all mitigate crosstalk at the cost of routing density.