cmos image sensor cis

A CMOS image sensor converts incident photons into a per-pixel electrical signal by pairing a pinned photodiode with a transfer-gate readout chain, and every process choice — implant profile, trench isolation, color-filter and microlens stack — feeds directly into two competing pixel metrics: quantum efficiency, how much incident light becomes signal charge, and dark current, how much unwanted charge accumulates with no light present at all. Unlike a discrete photodiode, a CIS pixel is fabricated pixel by pixel across a dense array, so a process variation invisible on a single device becomes a visible row or column defect once repeated across millions of sites. **The pinned photodiode fully depletes under reverse bias and pins its surface potential near the substrate potential, and that pinning is what suppresses the surface-state dark current that would otherwise dominate a conventional photodiode.** A shallow p+ implant sits directly above the n-type photodiode region, forming a p-n-p structure that depletes completely at a modest reverse bias and eliminates the direct interface between the photodiode depletion region and the Si-SiO2 boundary where trap states generate leakage carriers. Implant energy and dose set both the depletion depth, typically 0.3 to 0.5 µm below the surface, and the pinning voltage, commonly held within a few tenths of a volt of 0 V; a rapid thermal anneal activates the implant and repairs lattice damage without letting dopant diffusion blur the profile. **The transfer gate switches the path between the pinned photodiode and the floating diffusion, and its potential profile determines charge transfer efficiency far more than any other single structure in the pixel.** A TX pulse, typically 2.8 V high for roughly 50 ns and returning to a negative or ground low level between exposures, drives photogenerated charge from the photodiode over the channel potential barrier into the floating diffusion in a single transfer event; incomplete transfer leaves residual charge behind and shows up downstream as image lag. Gate length near 250 nm and an equivalent oxide thickness of roughly 6 nm are tuned jointly with the photodiode-to-gate spacing so the channel potential slopes monotonically toward the floating diffusion. **Floating diffusion capacitance sets conversion gain, and a smaller node reads out a larger voltage per transferred electron at the direct cost of full-well headroom.** Reset clears the floating diffusion to a reference level, commonly 3.3 V, immediately before each transfer event, and correlated double sampling subtracts the reset-level read from the signal-level read to cancel reset noise and most fixed-pattern offset; the node is kept physically small and shielded from the transfer gate's fringing field so gain stays predictable across the array. A pixel optimized for low-light sensitivity favors a smaller floating diffusion and higher gain, while one optimized for dynamic range favors a larger node and lower gain. **Deep trench isolation blocks both optical and electrical crosstalk between neighboring pixels, and its trench geometry is a direct trade-off against dark current generated at the trench sidewall.** A DTI trench etched to roughly 120 nm wide and 3 to 4 µm deep, filled with a dielectric liner and a metal or polysilicon core, stops obliquely incident photons and diffusing minority carriers from crossing into an adjacent pixel's photodiode; front-side DTI is formed before the interconnect stack while back-side DTI is etched from the illuminated side after thinning. Every trench sidewall introduces fresh interface states from the etch and fill process, so a hydrogen-rich passivation anneal after trench fill is essential to suppress the additional dark current those states would otherwise generate. **Dark current traces back to interface and bulk trap states, and DLTS is the metrology of choice because it separates trap energy level and density rather than reporting a single leakage number.** A trap level measured at roughly 0.3 to 0.4 eV below the conduction band edge is characteristic of trench-sidewall or gate-edge damage rather than bulk defects, and tracking that signature across process splits lets an integration team attribute a dark-current shift to a specific step. Hall effect measurements confirm carrier concentration and mobility in the photodiode and floating-diffusion implants against target doping, XPS and SIMS depth profiling verify that the pinning implant and anneal produced the intended dopant profile at the surface and interface, and four-point probe measurements confirm sheet resistance on the floating-diffusion and transfer-gate polysilicon. **Quantum efficiency is set as much by the optical stack above the silicon as by the photodiode itself, and a microlens over each color-filter element exists purely to recover light that would otherwise miss the shrinking photodiode.** A color filter array, patterned in a repeating red-green-blue mosaic roughly 0.6 µm thick per layer, and a microlens array reflowed above it focus incident light onto a photodiode that occupies a shrinking fraction of the pixel footprint as pitch scales; ellipsometry verifies dielectric and passivation stack thickness through the optical build so the microlens focal length and color-filter transmission stay within specification. Backside illumination removes the metal interconnect stack from the light path, lifting peak quantum efficiency by roughly 15% relative to a front-side illuminated pixel, and chief ray angle correction at the array edge, where incident light arrives at up to roughly 28° from normal, keeps edge-pixel sensitivity close to center-pixel sensitivity. **Pixel pitch has scaled from roughly 5.6 µm in early consumer sensors down to 1.4 µm and, in mobile-class arrays, below 0.8 µm, and every scaling step tightens the trade-off between full-well capacity and dark current density.** A smaller pixel collects fewer photogenerated electrons at saturation, so full-well capacity and dynamic range fall unless pixel binning or dual-conversion-gain readout partially recovers headroom in software; DTI trench width and pinning implant depth must both shrink proportionally, which is why interface-state control through anneal and passivation is a harder problem at 0.8 µm pitch than at 5.6 µm. Electro-optical qualification closes the loop: Keithley source-measure units sweep dark current and photocurrent I-V curves across the array, Keysight pulse generators characterize transfer-gate timing margin, and NIST-traceable optical power references anchor the quantum-efficiency measurement. The table below places the major pixel structures alongside what each one controls and how it fails when mis-set: | Structure | Typical value | What it controls | Failure mode if mis-set | |---|---|---|---| | Pinned photodiode implant | 0.3–0.5 µm depth | full depletion, dark current suppression | incomplete pinning, high dark current | | Transfer gate | 250 nm Lg, 2.8 V / 50 ns pulse | charge transfer efficiency | image lag, residual charge | | Floating diffusion | reset to 3.3 V | conversion gain, readout noise | gain mismatch, blooming | | Deep trench isolation | 120 nm wide, 3–4 µm deep | optical/electrical crosstalk | pixel-to-pixel leakage, dark current | | Passivation anneal | hydrogen-rich, staged | trench sidewall trap density | elevated dark current, DLTS-flagged traps | | Microlens / color filter | ≈0.6 µm CF, reflowed lens | quantum efficiency, CRA correction | light loss, edge QE roll-off | ```flowchart p-epi wafer prep → Pinned photodiode implant + anneal → Transfer gate formation (poly, gate oxide) → Floating diffusion implant → Deep trench isolation etch and fill → Sidewall passivation anneal (hydrogen) → Interlayer dielectric and planarization → Color filter array patterning → Microlens formation and reflow → Electro-optical test (dark current, QE, CTE via Keithley, Keysight) → Trap and interface verification (DLTS, XPS, SIMS, Hall effect) → Pixel array qualification and wafer release ``` Read the CMOS image sensor pixel through a pixel-sensitivity engineering lens: every structure inside the pixel — pinned photodiode, transfer gate, floating diffusion, deep trench isolation, color filter, microlens — exists to move one of two numbers, quantum efficiency or dark current, without moving the other the wrong way, and pixel pitch scaling from 5.6 µm down to 0.8 µm has made that trade-off progressively less forgiving. A pinning implant characterized at 0.3 to 0.5 µm depth and a transfer gate characterized at 250 nm with a 50 ns pulse define a fixed operating point for a given process node; shrinking pitch without re-characterizing both moves the pixel off that point rather than simply scaling it down. Deep trench isolation and its passivation anneal exist because shrinking pitch pushes photodiodes physically closer together, trading a harder trench-etch and interface-control problem for tighter optical and electrical isolation. Hall effect, DLTS, XPS, SIMS, four-point probe, and ellipsometry close the metrology loop on implant, interface, and optical-stack quality, while Keithley and Keysight electro-optical test, anchored to NIST-traceable references, confirms that the modeled sensitivity and dark current match what the array actually delivers.