cmos rf switch process

CMOS RF switch process integrates a silicon-on-insulator stack with series-stacked field-effect transistors to route radio-frequency signals between antenna, filter, and transceiver paths while adding minimal loss and holding off unwanted power leakage into blocked branches. The device sits at the crossroads of a semiconductor fabrication problem and a systems-level radio problem: every layer of buried-oxide thickness, every point of body-contact resistance, and every finger in the series stack shows up directly in insertion loss, isolation, and linearity numbers that a radio designer measures with a vector network analyzer. Unlike a digital logic transistor, whose designer mostly cares about drive current and leakage, an RF switch transistor is judged on how little it perturbs a signal when it is on and how completely it blocks that signal when it is off, and the same silicon-on-insulator platform that gives digital designers low parasitic capacitance is what gives the RF switch its low insertion loss and high isolation in the first place. **The buried oxide layer isolates the RF switch's top-silicon device film from the low-resistivity substrate below it, and that isolation is what keeps parasitic capacitance and substrate coupling losses from eating into insertion loss at gigahertz frequencies.** A typical stack pairs a 70 nm top-silicon film with a 145 nm buried oxide over a handle wafer specified at roughly 2 MΩ·cm resistivity, and thinner top-silicon combined with a higher-resistivity handle both push insertion loss down at the cost of a harder body-contact resistance target. Handle-wafer resistivity is not free to push arbitrarily high, either, because trap-rich or high-resistivity substrates interact with the buried-oxide interface to generate harmonic distortion through a parasitic surface-conduction layer, so process engineers frequently add a polysilicon trap-rich layer beneath the BOX specifically to suppress that mechanism before it ever reaches the linearity test. **Series-stacking multiple FETs between the RF input and output divides the blocking voltage across several devices, and the number of fingers in the stack is set directly by how much RF power the switch must handle without breakdown.** An 8-finger series stack with a 180 nm gate length and roughly 4 nm equivalent oxide thickness is a common configuration, and the resulting Ron·Coff figure of merit near 180 fs captures the fundamental trade-off between on-resistance and off-capacitance that no amount of layout optimization can escape. Adding fingers to the stack raises the voltage each device can block and therefore raises the RF power the switch can handle, but each added finger also adds series on-resistance and gate-drive routing overhead, so the finger count is chosen against a specific power-handling target rather than maximized on its own, and gate width is tuned in parallel so total Ron per finger stays low enough to hold insertion loss inside its budget. **Insertion loss and isolation move in opposite directions as gate width and stack height change, so every RF switch process defines a loss-isolation frontier rather than a single optimal point.** A representative part shows insertion loss near 0.35 dB and isolation near 45 dB at 2 GHz, degrading to roughly 0.6 dB insertion loss and 33 dB isolation at 6 GHz, and a designer choosing between switch variants is really choosing a position along that frontier for a specific frequency band. Isolation degrades with frequency mainly because off-state capacitance provides an easier leakage path as reactance falls, while insertion loss climbs more gradually with frequency through skin-effect and dielectric-loss mechanisms in the routing above the switch, so a switch qualified at 2 GHz cannot simply be assumed to hold its numbers at 6 GHz without a fresh sweep across the full band. **Linearity determines whether the switch distorts a strong adjacent-channel signal enough to desensitize the receiver, and IIP3 is the figure that radio engineers track most closely.** Third-order input intercept near 35 dBm at 2 GHz with third-harmonic distortion held below -40 dBc is typical for a body-contacted SOI switch, and control-voltage swing between 0 V and 3.3 V across the gate stack must be sized so the FETs stay in their intended operating region across that full power range. Harmonic distortion in a series-stack switch usually originates in the nonlinear off-state capacitance of the stacked FETs rather than in the on-state channel, which is why stack uniformity across all 8 fingers matters as much as any single device's individual linearity, and even a single mismatched finger in the stack can dominate the measured HD3 number. **Body contact resistance controls how effectively the switch dissipates trapped charge and stabilizes the floating-body potential under RF drive, and an under-designed contact shows up as compression and self-heating long before the device reaches its rated power.** A body contact resistance near 40 ohm with contact pitch around 5 µm is a common target, and RF power handling up to 10 W with switching time under 1 µs, typically 200 ns, rounds out the specification a module designer checks before qualifying the part. Floating-body effects are the reason body contact cannot simply be omitted: without a low-resistance path to bleed off impact-ionization charge, the body potential drifts with RF drive level and modulates threshold voltage in a way that shows up as unwanted amplitude-to-phase distortion, so the body-contact pitch is a linearity lever every bit as much as it is a resistance spec. **Process verification for an RF switch leans on electrical and materials metrology working together, since insertion loss and isolation numbers only make sense once resistivity, mobility, and interface quality are independently confirmed.** Four-point probe measurement tracks body-contact sheet resistance, Hall effect measurement confirms channel mobility near 1350 cm²/V·s, SIMS dopant profiling checks the body implant depth, and AFM surface-roughness scans below 0.3 nm RMS confirm buried-oxide interface quality ahead of the RF characterization step. None of these measurements substitutes for another: sheet resistance from a four-point probe cannot reveal a mobility problem, and a clean Hall effect mobility number cannot catch a rough BOX interface that only AFM will flag, so a mature RF switch flow runs all four checks on every lot rather than sampling one and inferring the rest. **Final RF characterization ties the whole process back to system-level requirements, because a switch that passes every wafer-level DC test can still fail an S-parameter or linearity spec once it is packaged next to a filter.** S-parameters are measured on a Keysight vector network analyzer to 20 GHz, body bias is swept on a Keithley source-measure unit in 0.1 V steps against NIST-traceable references, and the switch is then co-integrated with bulk acoustic wave filters in the RF front-end module where its loss and linearity budget gets spent alongside the filter's own insertion loss. A bulk acoustic wave filter typically contributes its own 1.5 to 2.5 dB of passband insertion loss, so a system budget that allocates only 0.5 dB total to the switch leaves the filter designer very little room, and this coupling is exactly why RF switch and BAW filter teams increasingly co-optimize rather than treat each block as an independent black box. | Structure | Typical value | What it controls | Failure mode | |---|---|---|---| | Top-Si film | 70 nm | Substrate coupling, loss | Excess insertion loss | | Buried oxide (BOX) | 145 nm | Isolation from handle wafer | Substrate leakage, higher loss | | Series-stack FET | 8 fingers, 180 nm gate | Power handling, Ron·Coff FOM | Breakdown, gain compression | | Body contact | 40 ohm, 5 µm pitch | Charge dissipation, linearity | Self-heating, harmonic distortion | | Control voltage swing | 0 to 3.3 V | FET on/off state | Incomplete switching | | BAW filter co-integration | RF front-end module | System loss/linearity budget | Module-level spec failure | ```flowchart SOI wafer prep (BOX + top-Si) → Body contact implant and anneal → Gate stack formation (poly, EOT 4 nm) → Series-stack FET fabrication (8-finger, 180 nm gate) → Body contact metallization → RF characterization (Keysight VNA, S-parameters to 20 GHz) → Linearity test (IIP3, HD3 via Keithley SMU) → BAW filter co-integration → RF front-end module assembly → NIST-traceable calibration and qualification → Wafer and module release ``` Read the CMOS RF switch process through an RF loss-linearity engineering lens: a 70 nm top-silicon film over a 145 nm buried oxide, an 8-finger 180 nm series stack with Ron·Coff near 180 fs, a 40 ohm body contact on a 5 µm pitch, and IIP3 near 35 dBm at 2 GHz are not independent numbers but five faces of the same loss-isolation-linearity trade-off, verified end to end with four-point probe, Hall effect, SIMS, AFM, Keysight, Keithley, and NIST-traceable metrology before the switch is co-integrated with BAW filters in the RF front-end module.