cmp

Chemical mechanical planarization is the only semiconductor manufacturing step that simultaneously exploits chemistry and abrasion to remove material, and it is the only step whose purpose is not to add a feature but to erase topography so that the next feature can be printed. Every interconnect layer in a modern logic chip — fourteen or more metal levels at the 3 nm node — begins life as a blanket film that must be polished flat before the stepper can hold focus for the layer above. Without CMP there is no damascene copper, no shallow-trench isolation, no planar gate stack, and no multilayer wiring at all. The process is deceptively simple in concept — press the wafer face-down against a rotating polyurethane pad while feeding a slurry of nanometre-scale abrasive particles suspended in a reactive liquid — yet the physics spans contact mechanics, tribology, electrochemistry, colloidal science, and fluid dynamics. Every hard problem in CMP is a different way of asking: how do you remove exactly the right amount of material from every point on the wafer, stop precisely at the target interface, and leave the surface free of scratches, particles, and chemical residue? **The Preston equation is the foundational model of CMP removal rate.** The material removal rate (MRR) at any point on the wafer is given by $\text{MRR} = k_p \times P \times V$, where $P$ is the local contact pressure between wafer and pad, $V$ is the relative velocity of the wafer surface against the pad, and $k_p$ is the Preston coefficient — an empirical constant that absorbs the effects of slurry chemistry, abrasive size, pad properties, and temperature. The Preston equation predicts that high spots on the wafer, which bear more pressure per unit area, polish faster than low spots, providing the self-levelling action that drives planarisation. In practice $k_p$ is not constant: it depends on the chemical state of the surface, the slurry pH, the pad condition, and the temperature, so the equation is best understood as a linearised approximation valid over a limited process window. Typical Preston coefficients for oxide CMP with colloidal silica slurry at pH 10–11 fall in the range $1 \times 10^{-13}$ to $5 \times 10^{-13}\;\text{Pa}^{-1}$, while copper CMP coefficients are often an order of magnitude higher because the oxidised copper surface is softer. Preston Equation and Removal-Rate Mechanics Preston Equation MRR = kp × P × V kp = Preston coefficient (Pa⁻¹) P = contact pressure (Pa) V = relative velocity (m/s) Oxide kp ≈ 1–5 × 10⁻¹³ Pa⁻¹ Cu kp ≈ 1–5 × 10⁻¹² Pa⁻¹ (10× higher) Self-Levelling Action High spot → more P → faster removal After polish → flat surface Stribeck Curve (friction regimes) Sommerfeld number (ηV/P) Friction coeff. (μ) Boundary Mixed Hydrodyn. high wear direct contact low wear fluid film CMP operates here (mixed) Contact Mechanics Hertzian contact at pad asperities • Pad asperity radius: 5–50 µm • Contact area: 0.1–1% of wafer • Real pressure at contacts: 10–100 MPa • Applied pressure: 1–7 psi (7–48 kPa) Greenwood-Williamson model: Real contact area ∝ P / (E* × σ_asperity) More asperities → more uniform removal **The Stribeck curve divides CMP into three tribological regimes that determine removal rate and defectivity.** The dimensionless Sommerfeld number $S = \eta V / P$ (where $\eta$ is slurry viscosity, $V$ is velocity, and $P$ is pressure) determines whether the wafer–pad interface operates in the boundary regime (direct asperity contact, high removal, high scratching), the mixed regime (partial fluid film, moderate removal, acceptable defectivity), or the hydrodynamic regime (full fluid film, near-zero removal). Production CMP operates in the mixed regime: enough contact to remove material, enough fluid film to lubricate and prevent catastrophic scratching. A slurry that is too viscous or a velocity that is too high pushes the process into hydroplaning, where the wafer lifts off the pad and removal rate collapses. **Hertzian contact mechanics governs the real contact area between pad asperities and the wafer.** The polyurethane pad surface is not smooth — it is populated with asperities whose tip radii range from 5 to 50 µm. The Greenwood–Williamson model predicts that the real contact area is a small fraction (0.1–1%) of the nominal wafer area, concentrating the applied pressure (typically 1–7 psi, or 7–48 kPa) into local contact stresses of 10–100 MPa. These high local stresses are what enable mechanical abrasion even at modest applied loads. Pad conditioning with a diamond disk regenerates the asperity population; without conditioning, the asperities deform plastically and the pad glazes, causing removal rate to decay exponentially with polish time. **CMP tool architecture consists of five subsystems: carrier head, platen, pad, slurry delivery, and conditioner.** The carrier head holds the wafer face-down with a retaining ring and applies zone-based pneumatic pressure through a flexible membrane — typically five to seven concentric zones whose pressures can be independently adjusted from 0 to 7 psi. The platen is a large rotating table (diameter 500–760 mm) on which the polishing pad is mounted. The pad is a closed-cell polyurethane foam (the most common being the Dow/DuPont IC1000, 1.2 mm thick, Shore D hardness 52–62) with machined grooves (concentric, K-groove, or XY pattern) that transport slurry to the wafer–pad interface. The slurry delivery system meters slurry to the pad centre at a controlled flow rate (typically 150–300 mL/min) and temperature. The in-situ conditioner — a diamond-grit disk rotating on a sweep arm — continuously dresses the pad to maintain a stable asperity height distribution and prevent glazing. CMP Tool Anatomy Polishing Pad (IC1000) polyurethane, Shore D 52–62, K-groove pattern Rotating Platen (30–120 rpm) Carrier Head membrane (5–7 pressure zones) wafer (face down) ring Downforce (1–7 psi) 30–120 rpm Slurry Supply 150–300 mL/min temp controlled slurry flow Conditioner diamond-grit disk sweeps across pad Slurry: SiO₂/CeO₂ abrasive + H₂O₂ + pH buffer Pad: IC1000 or similar porous polyurethane Conditioner: regenerates pad asperities **Zone-based carrier pressure control is the primary knob for within-wafer uniformity.** Modern carrier heads divide the wafer backside into five to seven concentric annular zones, each backed by an independent air bladder. If the edge removal rate runs high — the classic "fast edge" problem caused by the retaining ring loading the pad near the wafer periphery — the outer-zone pressure is reduced relative to the centre zones. Conversely, if the centre polishes slowly because the pad is stiffer near the carrier axis, the centre-zone pressure is increased. The retaining ring pressure itself is a separate control: it pre-loads the pad outside the wafer edge to smooth the pressure discontinuity at the wafer boundary. A well-tuned five-zone carrier can achieve within-wafer non-uniformity (WIWNU, defined as the standard deviation of removal rate divided by the mean, expressed as a percentage) below 2% on blanket films. **Polishing pad groove geometry determines slurry transport and debris removal.** The three common groove patterns — concentric circular, K-groove (radial + concentric intersecting), and XY grid — trade off slurry residence time against debris evacuation. Concentric grooves provide the most uniform slurry distribution but trap debris in the grooves, increasing scratch defects. K-grooves offer better debris clearance at the cost of slight removal-rate anisotropy. XY grids provide the best debris evacuation for aggressive metal-CMP steps but consume more slurry. The groove depth is typically 400–600 µm, and the groove pitch is 1.5–3 mm; as the pad wears during its lifetime (typically 300–600 wafers), the effective groove depth decreases and the process engineer must track pad life to avoid groove depletion, which sharply degrades uniformity. **Dishing is the defining planarisation defect in metal CMP.** When copper fills a wide trench (above approximately 10 µm line width), the compliant pad conforms to the recessed metal surface after the field oxide clears, continuing to polish the copper below the target plane. The resulting concavity in the metal line is called dishing, and it increases with trench width, pad compliance, over-polish time, and copper-to-barrier selectivity. For a 100 µm wide copper line with a typical IC1000 pad and 30% over-polish, dishing can exceed 50 nm — a catastrophic thickness loss for a 100 nm target metal thickness. Reducing dishing requires stiffer pads (higher Shore D hardness), lower copper-to-barrier selectivity (so the barrier layer acts as a local stop), shorter over-polish time, and design-rule restrictions on maximum metal width. Dishing, Erosion, and Pattern-Density Effects Dishing metal recesses below oxide in wide trenches oxide Cu (wide trench) dishing target plane Dishing ∝ trench width × pad compliance 100 µm trench → 50+ nm dishing typical Erosion oxide loss in dense metal arrays target actual erosion Erosion ∝ effective pattern density Dense arrays lose 20–40 nm oxide at 50% density Pattern Density Drives Both Dishing and Erosion Effective pattern density (%) Loss (nm) 0 20 40 60 80 100 dishing (isolated lines) erosion (dense arrays) Dummy Fill Mitigation • Insert dummy metal in low-density regions • Target effective density: 30–70% • Reduces max dishing from 50+ nm to <15 nm • EDA tools auto-fill during layout finishing • Must avoid coupling to active signals **Erosion is the complementary defect to dishing and dominates in dense metal arrays.** In a region where copper lines are closely spaced (high effective pattern density, above 50%), the pad cannot distinguish individual lines from the bulk and treats the array as a continuous copper surface. The entire oxide–copper array polishes faster than the surrounding isolated oxide field, causing the oxide surface to recede below the target plane. Erosion of 20–40 nm is typical at 50% pattern density with 30% over-polish. The combined effect of dishing (worst at low density, wide lines) and erosion (worst at high density, narrow pitch) creates a topography map across the die that the CMP process engineer must flatten to within 10–15 nm for advanced-node lithography. **Dummy fill is the design-level solution to pattern-density–induced CMP non-uniformity.** By inserting non-functional metal tiles in low-density regions, the effective pattern density is raised to a target window of 30–70% across the die. This reduces the dishing/erosion contrast and improves global planarity after CMP. Modern EDA tools (Calibre, IC Validator) insert dummy fill automatically during layout finishing, obeying spacing rules that prevent parasitic coupling to active signals. Without dummy fill, a logic die with density ranging from 5% (pad region) to 80% (SRAM array) would show 50+ nm planarity variation after CMP; with fill, the variation drops below 15 nm. **Copper CMP is a three-step process: bulk copper removal, barrier clear, and buff.** The first step (Step 1) uses a high-removal-rate slurry — typically colloidal silica or alumina abrasive at pH 3–5 with hydrogen peroxide ($\text{H}_2\text{O}_2$) as the oxidiser and benzotriazole (BTA) as a copper corrosion inhibitor — to remove the overburden copper down to near the barrier layer. The second step (Step 2) uses a barrier-removal slurry, often with a ceria abrasive at neutral to alkaline pH, to clear the Ta/TaN barrier from the field while minimising oxide erosion. The third step (Step 3) is a short buff polish on a soft pad with a dilute slurry to remove residual particles and reduce surface roughness below 0.3 nm RMS. The three-step approach is necessary because no single slurry can simultaneously achieve the high copper removal rate needed for throughput, the selectivity needed for barrier clearing, and the low-defect finish needed for the next deposition. Copper Damascene CMP: Three-Step Process Step 1: Bulk Cu remove overburden copper Before Cu overburden Slurry: • SiO₂ or Al₂O₃ abrasive • pH 3–5 (acidic) • H₂O₂ oxidiser • BTA inhibitor MRR: 400–800 nm/min Selectivity: Cu:oxide > 50:1 Step 2: Barrier clear Ta/TaN from field After Step 1 Ta/TaN barrier Slurry: • CeO₂ abrasive (high oxide selectivity) • pH 7–9 (neutral to alkaline) • Low H₂O₂ concentration • Surfactant for Cu passivation MRR: 30–80 nm/min (barrier) Selectivity: barrier:oxide ≈ 3–5:1 Step 3: Buff defect reduction, surface finish Final planar surface ✓ Process: • Soft pad (Politex or similar) • Dilute slurry, low pressure • Removes residual particles • Surface roughness < 0.3 nm RMS MRR: 5–20 nm/min Target: zero scratches, zero residue Cu CMP Chemistry: Oxidise → Passivate → Abrade cycle 1. H₂O₂ oxidises Cu surface → CuO (softer than metallic Cu) 2. BTA forms passivation film on recessed areas → protects from corrosion 3. Abrasive particles mechanically remove CuO from high spots only Without BTA: isotropic corrosion → poor planarity. Without H₂O₂: metallic Cu too hard → low MRR. **Benzotriazole (BTA) is the key chemical that makes copper CMP planar rather than isotropic.** In the absence of a corrosion inhibitor, the oxidiser ($\text{H}_2\text{O}_2$) would attack all exposed copper surfaces equally — high spots and trenches alike — producing uniform etching with no planarisation. BTA forms a thin polymeric Cu-BTA complex on the copper surface that is resistant to chemical attack but mechanically weak. At high spots, where the pad makes direct contact, the abrasive particles shear off the BTA film and expose fresh copper for oxidation and removal. In recesses, where the pad cannot reach, the BTA film remains intact and protects the copper from dissolution. This differential protection — mechanical removal of the passivation layer only at high points — is the mechanism that converts CMP from a uniform etch into a planarising process. **Tungsten CMP for contact and via plugs uses a fundamentally different chemistry from copper CMP.** The W-CMP slurry is typically an acidic (pH 2–4) solution containing potassium iodate ($\text{KIO}_3$) or ferric nitrate ($\text{Fe(NO}_3)_3$) as the oxidiser, with colloidal silica abrasive. The oxidiser converts the tungsten surface to a soft tungsten oxide ($\text{WO}_3$) that the abrasive can mechanically remove. Unlike copper CMP, tungsten CMP does not require a corrosion inhibitor because the tungsten oxide layer is self-passivating — it forms a stable film that limits further oxidation. The selectivity of W-CMP slurry to the underlying oxide stop layer must exceed 20:1 to prevent excessive dielectric loss. Tungsten CMP is used at the contact level (W plug filling contact holes to the transistor) and at via levels where tungsten vias connect metal layers. **Oxide CMP for shallow-trench isolation (STI) uses ceria-based slurry with extraordinarily high selectivity.** The STI process requires removing the deposited oxide overfill from the trenches while stopping precisely on the silicon nitride pad layer that caps the active areas. A ceria ($\text{CeO}_2$) slurry achieves oxide-to-nitride selectivity exceeding 50:1 through a mechanism called the "chemical tooth" — the ceria particle surface forms temporary Ce-O-Si bonds with the silica surface, weakening the Si-O network and enabling removal at far lower mechanical forces than silica-based polishing. On silicon nitride, these bonds do not form efficiently, providing the selectivity needed to stop on the nitride. This high selectivity means that STI-CMP is effectively a self-stopping process: once the nitride is exposed, the removal rate drops by more than an order of magnitude. Endpoint Detection Methods Motor Current friction change at layer transition Polish time Current (A) endpoint Cu polishing barrier Optical (In-Situ) reflectance through pad window window light in reflected interference oscillations → thickness Eddy Current sheet resistance change during polish coil in platen Cu film on wafer clear point thick Cu cleared Endpoint Method Comparison Method Principle Best For Resolution Limitation Motor current Friction (torque) change Cu → barrier transition Wafer-level avg No spatial info Optical (ISR) Reflectance / interference Oxide thickness, Cu clear Per-zone, ~1 nm Needs pad window Eddy current Sheet resistance (Rs) Metal thickness in real time Per-zone, ~2 nm Metal films only Acoustic Vibration spectrum shift Hard-stop transitions Wafer-level avg Low sensitivity **Endpoint detection determines when to stop polishing and is the difference between a good wafer and scrap.** Under-polishing leaves residual metal that shorts adjacent lines; over-polishing wastes dielectric thickness and worsens dishing and erosion. Three endpoint methods dominate production CMP. Motor-current endpoint detects the change in platen or carrier torque when the wafer transitions from one material to another — the friction coefficient between copper and the pad differs from that between barrier metal and the pad, producing a measurable current step. Optical (in-situ reflectometry, ISR) shines broadband light through a transparent window in the pad and measures the reflectance spectrum of the wafer surface in real time; interference fringes track oxide thickness with ~1 nm resolution, and a sharp reflectivity change signals metal clearing. Eddy-current sensing embeds a coil in the platen beneath the pad and measures the change in impedance caused by the conductive metal film on the wafer; as the metal thins, the sheet resistance rises and the eddy-current signal tracks the remaining thickness with ~2 nm resolution and zone-level spatial information. **Post-CMP cleaning is as critical as the polish itself.** Slurry residue — abrasive particles, metal ions, BTA, and organic contaminants — left on the wafer surface after polishing can nucleate defects, increase contact resistance, and poison gate dielectrics. The post-CMP clean typically comprises a megasonic or brush-scrub step with dilute ammonium hydroxide ($\text{NH}_4\text{OH}$) to dislodge particles, a dilute hydrofluoric acid (dHF) or citric-acid dip to remove metal-ion contamination, and a final DI-water rinse. For copper CMP, an additional step with a proprietary organic acid (e.g., Entegris or Dupont cleaning solutions) removes the BTA residue without corroding the exposed copper. Brush-scrub tools (typically PVA brush with megasonic assist) physically sweep particles from the surface; brush pressure, rotation speed, and chemistry must be co-optimised to avoid re-depositing the particles they remove. Post-CMP defect targets for advanced nodes are below 0.05 defects/cm² at the 30 nm defect-size threshold. CMP Slurry Chemistry and Pad Technology Abrasive Particle Types Fumed SiO₂ 30–100 nm irregular shape aggressive Colloidal SiO₂ 20–70 nm spherical low defect CeO₂ (Ceria) 50–200 nm "chemical tooth" high selectivity Fumed SiO₂ → oxide ILD, W CMP (aggressive) Colloidal SiO₂ → Cu CMP step 1, buff (gentle) CeO₂ → STI CMP, barrier step (selective stop) All: zeta potential must match wafer charge for removal Pad Types and Groove Patterns Hard Pad (IC1000) Shore D 52–62, 1.2 mm Steps 1–2: planarity Soft Pad (Politex) Shore A 50–70, compliant Step 3: buff, low defect Groove patterns: Concentric K-groove XY grid Diamond Disk Conditioning In-situ conditioning: diamond grit disk sweeps pad during polish → regenerates asperities → stable MRR Without conditioning: pad glazes → MRR decays 30–50% within 25 wafers → WIWNU degrades to >5% Conditioning aggressiveness: cut rate 2–5 µm/hr, disk lifetime 500–1000 hr, grit size 40–100 µm Key Slurry Chemical Roles Oxidiser (H₂O₂, KIO₃): softens metal surface Inhibitor (BTA): passivates recesses pH buffer (KOH, NH₄OH): controls zeta potential Surfactant: particle dispersion stability Complexant (citric, glycine): Cu removal Biocide: prevents microbial growth **Slurry abrasive selection fundamentally determines removal rate, selectivity, and defectivity.** The three dominant abrasive materials — fumed silica, colloidal silica, and ceria — serve different CMP applications. Fumed silica particles (30–100 nm, irregular chain-aggregate morphology, produced by flame hydrolysis of SiCl₄) are mechanically aggressive and are used for oxide ILD planarisation and tungsten CMP. Colloidal silica particles (20–70 nm, spherical, grown by Stöber synthesis) are gentler and produce fewer scratches, making them the preferred abrasive for copper CMP step 1 and buff steps. Ceria particles (50–200 nm) provide the "chemical tooth" mechanism for high-selectivity oxide-to-nitride polishing in STI CMP. The zeta potential of the particles (controlled by pH) determines whether they are attracted to or repelled from the wafer surface; at the isoelectric point of silica (pH ~2), particles aggregate and scratch the surface, so production slurries operate at pH 9–11 (for oxide CMP) or pH 3–5 (for copper CMP) where colloidal stability is high. **Pad conditioning with a diamond disk is not optional — it is the process control that prevents removal-rate drift.** An unconditioned pad glazes within 20–30 wafers: the polyurethane asperities deform plastically under the polishing load, the surface becomes smooth, the real contact area increases, and paradoxically the removal rate drops because the individual asperity contact pressure decreases. In-situ conditioning — where the diamond disk sweeps the pad during polishing — regenerates the asperity population continuously, maintaining a steady-state surface roughness and a stable removal rate. The conditioning disk is a nickel-brazed or electroplated disk studded with synthetic diamond grains of 40–100 µm size. The disk cut rate (2–5 µm/hr of pad material removed) determines the conditioning aggressiveness; too little conditioning allows glazing, too much wastes pad life. Diamond disk lifetime is typically 500–1,000 hours of conditioning time, after which the grit dulls and removal-rate stability degrades. | Parameter | Oxide CMP (ILD) | STI CMP | Cu CMP Step 1 | Cu CMP Step 2 (barrier) | W CMP | |---|---|---|---|---|---| | Abrasive | fumed SiO₂ | CeO₂ | colloidal SiO₂ | CeO₂ | fumed SiO₂ | | pH | 10–11 | 4–7 | 3–5 | 7–9 | 2–4 | | Oxidiser | none | none | H₂O₂ (1–3%) | low H₂O₂ | KIO₃ or Fe(NO₃)₃ | | Inhibitor | none | none | BTA | surfactant | none | | MRR (nm/min) | 200–400 | 150–300 | 400–800 | 30–80 | 200–400 | | Selectivity | oxide:nitride 3:1 | oxide:nitride >50:1 | Cu:oxide >50:1 | barrier:oxide 3–5:1 | W:oxide >20:1 | | Pad | IC1000 | IC1000 | IC1000 | IC1000 | IC1000 | | Endpoint | optical (ISR) | motor current + optical | eddy current + motor | eddy current | motor current | **The Sommerfeld number provides a dimensionless framework for comparing CMP processes across different tools and conditions.** Defined as $S = \eta V / P$ where $\eta$ is the dynamic viscosity of the slurry (typically 1–5 mPa·s), $V$ is the relative pad-wafer velocity (0.5–2.5 m/s), and $P$ is the applied pressure (7–48 kPa), the Sommerfeld number maps the process onto the Stribeck curve. Production CMP operates at $S \approx 10^{-6}$ to $10^{-5}$, firmly in the mixed lubrication regime. If $S$ increases (higher velocity or lower pressure), the process transitions toward hydrodynamic lubrication and removal rate drops precipitously. If $S$ decreases (higher pressure or lower velocity), the process enters boundary lubrication where direct pad-wafer contact dominates, removal rate is high but scratch defects become unacceptable. **Within-wafer non-uniformity (WIWNU) is the primary metric of CMP process quality.** WIWNU is defined as $\text{WIWNU}(\%) = \frac{\sigma_{\text{RR}}}{\bar{\text{RR}}} \times 100$, where $\sigma_{\text{RR}}$ is the standard deviation of removal rate across 49 or more measurement sites on the wafer and $\bar{\text{RR}}$ is the mean removal rate. Advanced-node specifications require WIWNU below 2% for blanket-film polishing and below 3% for patterned-wafer polishing. WIWNU is controlled primarily through carrier zone pressures, retaining ring pressure, pad conditioning uniformity, and slurry flow distribution. Wafer-to-wafer non-uniformity (WTWNU), defined similarly over sequential wafers, must be below 1.5% and is controlled by pad life tracking, slurry batch consistency, and conditioner disk state. CMP Applications Across the Semiconductor Process Flow FEOL CMP STI (Shallow Trench Isolation) CeO₂ slurry, nitride stop layer Selectivity: oxide:nitride > 50:1 Poly / Replacement Metal Gate Planarises gate stack before S/D implant Critical for FinFET gate height control MOL CMP W Contact / Via Plug KIO₃ oxidiser, SiO₂ abrasive Selectivity: W:oxide > 20:1 Co / Ru Contact (≤5 nm nodes) New slurry chemistries for Co, Ru Galvanic corrosion is key challenge BEOL CMP Cu Damascene (M1–M14+) 3-step: bulk Cu → barrier → buff Runs 30–50× per chip at 3 nm node ILD Planarisation Oxide/low-k levelling between metals Low-k fragility limits pressure to ≤2 psi Advanced Node Challenges (≤5 nm) • Low-k dielectrics (k < 2.5): fragile, crack under CMP pressure → max 1.5–2 psi, soft pads • Cobalt/ruthenium interconnects: galvanic corrosion with Cu, new slurry chemistries needed • Backside power delivery (BSPDN): requires CMP on thinned wafer (<5 µm Si) — extreme fragility Equipment Vendors Applied Materials: Reflexion LK Prime (market leader) Ebara: FREX series (strong in Japan/Asia) KCTECH / Hwatsing: emerging competitors Consumables Vendors CMC Materials: slurries, pads (IC1000 family) Fujimi / AGC: specialty slurries (ceria, barrier) DuPont / Entegris: post-CMP cleaning chemicals **Low-k dielectric CMP at advanced nodes demands fundamentally lower pressures and forces than oxide CMP.** Carbon-doped oxide (CDO, SiOCH) and porous low-k films with dielectric constant $k < 2.5$ are mechanically weak — their Young's modulus is 3–8 GPa compared to 72 GPa for thermal SiO₂ — and are prone to cracking, delamination, and cohesive failure under CMP loads. Process engineers must limit the applied pressure to 1.5–2 psi (10–14 kPa), use softer pads, and employ slurries with near-zero mechanical abrasion (so-called "chemical CMP" where the removal is dominated by dissolution rather than particle abrasion). The penalty is reduced removal rate (50–100 nm/min versus 200–400 nm/min for dense oxide) and longer polish times. **Cobalt and ruthenium CMP represent the frontier of interconnect-metal polishing.** At the 5 nm node and below, copper is being replaced by cobalt (for MOL contacts and local interconnects) and ruthenium (as a barrierless liner or direct-fill metal) because these metals do not require a thick barrier layer and offer better resistance scaling at narrow dimensions. However, cobalt and ruthenium present new CMP challenges: cobalt has a galvanic potential difference of ~0.4 V relative to copper, causing accelerated corrosion at Co-Cu junctions during polishing; ruthenium is chemically inert in most conventional slurries and requires strongly oxidising chemistries (periodate, $\text{NaIO}_4$, or ceric ammonium nitrate) to form a removable oxide. Both materials generate novel defect modes — cobalt stress corrosion cracking and ruthenium particle embedding — that require new slurry formulations and post-CMP cleaning protocols. **CMP consumable cost is the single largest component of CMP cost-of-ownership.** Slurry alone accounts for 40–50% of the CMP process cost, with pad and diamond conditioner contributing another 25–30%. A single 300 mm copper-CMP step consumes approximately 300–500 mL of slurry per wafer across the three steps; at slurry prices of 200–400 USD per litre, the slurry cost is 0.10–0.20 USD per wafer per CMP step. Multiplied by 30–50 CMP steps per chip at the 3 nm node, slurry cost alone reaches 3–10 USD per die. Pad cost contributes 0.03–0.05 USD per wafer-pass, and diamond conditioner cost adds 0.01–0.02 USD per wafer-pass. These consumable costs make CMP the highest-consumable-cost operation in the fab, incentivising slurry recycling, dilute-slurry processes, and point-of-use blending systems. **Planarisation efficiency and planarisation length define the fundamental capability of a CMP process.** Planarisation efficiency $E_p$ is the fraction of the initial step height that is removed in one polish step: $E_p = (h_0 - h_f) / h_0$, where $h_0$ is the initial step height and $h_f$ is the final step height. An ideal CMP process has $E_p = 1$ (complete planarisation); in practice, $E_p = 0.90$–0.98 depending on pattern density and feature size. The planarisation length $L_p$ is the lateral distance over which the pad can bridge a step and preferentially remove the high side. For an IC1000 pad, $L_p$ is typically 3–5 mm; features wider than $L_p$ are not planarised and must rely on within-feature levelling by the slurry chemistry. The pad modulus, pad thickness, and backing-layer compliance together determine $L_p$ — stiffer pads have longer planarisation lengths but also produce more dishing in narrow features. ```flowchart CMP Process Decision Flow Incoming wafer with deposited film │ ▼ ┌─ What material must be removed? ─────────────────────────┐ │ │ ▼ ▼ ▼ ▼ Excess Cu W plug fill Oxide overfill Low-k ILD (damascene) (contact/via) (STI or ILD) (k < 2.5) │ │ │ │ ▼ ▼ ▼ ▼ 3-step Cu CMP W CMP Oxide CMP Low-k CMP pH 3–5 pH 2–4 pH 10–11 pH 8–10 H₂O₂ + BTA KIO₃ no oxidiser minimal abrasive colloidal SiO₂ fumed SiO₂ CeO₂ (STI) chemical-dominant fumed SiO₂(ILD) ≤2 psi pressure │ │ │ │ ▼ ▼ ▼ ▼ Eddy current Motor current Optical (ISR) Optical + timer endpoint endpoint endpoint endpoint │ │ │ │ └────────────────────┴────────────────────┴─────────────────┘ │ ▼ Post-CMP clean (brush scrub + megasonic + dHF/citric + DI rinse) │ ▼ Defect inspection (target: < 0.05 defects/cm² at 30 nm threshold) │ ▼ Next deposition / lithography step ``` **The most common professional mistake in CMP is treating removal rate as a fixed parameter rather than a dynamic variable.** Removal rate drifts with pad age, conditioner disk wear, slurry batch variation, and retaining ring erosion. A process engineer who qualifies the recipe at 500 nm/min on a fresh pad and sets a fixed polish time of 60 seconds for a 500 nm copper overburden will find that by wafer 200 the removal rate has shifted to 450 nm/min (if conditioning is marginal) or 550 nm/min (if temperature rises with continuous use), and the fixed-time recipe now over-polishes or under-polishes. Closed-loop endpoint control — using in-situ eddy current or optical monitoring to determine polish completion in real time — replaces fixed-time recipes and is mandatory for advanced-node CMP. The endpoint signal, not the clock, determines when to stop. **CMP is performed on every wafer at every interconnect level, making it one of the highest-frequency process steps in the fab.** A 3 nm logic chip with 14 metal layers requires at least one CMP step per metal layer (copper damascene), plus STI-CMP, gate-CMP, contact-W-CMP, and multiple ILD planarisation steps — totalling 30–50 CMP operations per wafer. At a throughput of 20–40 wafers per hour per platen (with multi-platen tools running 3–5 platens), CMP tools are among the most heavily utilised equipment in the fab. Tool availability above 95% and consumable management (pad life, slurry shelf life, conditioner disk tracking) are critical for sustaining line yield. Read CMP through a *pressure-velocity-chemistry* lens rather than a *polishing-machine* lens: every quantitative outcome the process delivers — removal rate, uniformity, dishing, erosion, defectivity — is determined by the interplay of the Preston-equation variables ($k_p$, $P$, $V$), the tribological regime (Stribeck number $S = \eta V / P$), and the slurry chemistry (oxidiser, inhibitor, abrasive type, pH). The canonical example — 500 nm/min copper removal at 3 psi, 80 rpm, pH 4, colloidal silica, 1% $\text{H}_2\text{O}_2$, BTA, IC1000 pad, in-situ conditioned — changes its removal rate, selectivity, and defectivity if any one of these variables drifts, because the Preston coefficient $k_p$ is not a constant but a function of all of them simultaneously. Endpoint detection converts CMP from a timed etch into a controlled process; zone-based carrier pressure converts it from a single-point process into a profile-controlled process; and dummy fill converts it from a pattern-dependent process into a pattern-insensitive process. Every hard problem in CMP is a different way of asking: how do I keep $k_p \times P \times V$ constant everywhere on the wafer, stop at the right interface, and leave the surface clean?

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