co-packaged optics

Co-packaged optics (CPO) places the optical transceivers — the electrical-to-optical engines — onto the same package as the switch or accelerator ASIC, instead of in pluggable modules at the front panel. The whole point is to shrink the electrical link between the compute silicon and the light to millimeters, because that link is what now limits bandwidth and burns the power.\n\n**The problem is the electrical run, not the optics.** In a pluggable system, the ASIC's high-speed SerDes must drive a signal across centimeters of lossy board to a front-panel module before it ever becomes light. As data rates climb (100→200 Gb/s per lane), that copper run costs more equalization, more power, and more area. CPO removes it: the optical engine sits a few millimeters from the ASIC on a shared substrate, so the electrical hop is short, low-loss, and cheap — and the fiber, which has no such distance penalty, carries the signal the rest of the way.\n\n**What CPO buys you is beachfront bandwidth density and energy-per-bit.** The perimeter of a package is finite — 'beachfront' — and pluggable modules waste it on long electrical channels. By putting optics right at the die edge, CPO packs far more Gb/s across that edge and cuts the energy spent per bit moved, which is exactly the constraint on scaling switch radix and GPU-to-GPU fabrics. It is the packaging counterpart to the same shift silicon photonics enables on-die.\n\n| Aspect | Pluggable optics | Co-packaged optics |\n|---|---|---|\n| Optics location | front-panel module | on the ASIC package |\n| Electrical reach | cm across board | mm on substrate |\n| Energy/bit | higher (SerDes-dominated) | lower |\n| Bandwidth density | limited by faceplate | high (die-edge beachfront) |\n| Serviceability | field-swappable | harder — soldered/attached |\n\n```svg\n\n \n Co-packaged optics — move the optical engines onto the ASIC package, killing the long electrical run\n\n \n \n\n \n Pluggable optics (today)\n \n \n \n \n switch\n ASIC\n \n \n \n long electrical trace (SerDes, lossy)\n \n \n \n faceplate\n \n \n \n Bandwidth capped by SerDes reach across the board;\n the electrical link dominates the power budget.\n\n \n Co-packaged optics (CPO)\n \n \n shared package substrate\n \n \n switch /\n XPU ASIC\n \n \n \n \n \n \n optical\n engine\n optical\n engine\n \n \n \n \n \n \n mm-scale electrical hop\n \n \n \n \n \n Optics sit mm from the ASIC, so the electrical link is\n tiny — more bandwidth per edge (beachfront) at lower pJ/bit.\n\n```\n\n**The tradeoffs are serviceability and thermal/assembly risk.** A pluggable module can be swapped in the field; a co-packaged optical engine is attached to a costly ASIC package, so a single failure can jeopardize the whole assembly, and the laser dislikes sitting next to a hot processor. Known-good-die testing, laser reliability, fiber attach, and repair strategy are the gating problems — which is why CPO adoption tracks how well the packaging and photonics supply chains mature, not whether the bandwidth case is real.\n\nRead co-packaged optics through a quant lens rather than a form-factor lens: the deciding numbers are energy-per-bit and bandwidth-per-mm of package edge at a target lane rate. Pluggable optics pay a fixed copper tax that grows with data rate; CPO trades that for assembly and serviceability risk. The engineering call is where the pJ/bit and beachfront gains outrun the yield and repair cost — measured per platform, not assumed.

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