Complementary FET Cfet

# Complementary Field-Effect Transistor (CFET) Architecture & Physics

Complementary Field-Effect Transistor (CFET) technology is the foundational three-dimensional device architecture designed to succeed lateral Gate-All-Around (GAA) nanosheet transistors below the 1.5 nm and 1.0 nm (sub-10 Ångström) semiconductor nodes. In conventional planar CMOS and lateral GAA architectures, NMOS and PMOS transistors are arranged side-by-side across the silicon surface. This lateral configuration requires a wide physical separation zone—known as the n-to-p boundary spacing ($S_{NP} \approx 20\text{ to }35\,\text{nm}$)—to accommodate separate high-k metal gate (HKMG) workfunction metal stacks, isolation shallow trench isolation (STI), and source/drain epitaxy without dopant cross-contamination. This dead space consumes between $35\%\text{ and }50\%$ of the total standard cell layout area.

CFET breaks through this geometric scaling barrier by folding the CMOS pair vertically: stacking an NMOS nanosheet transistor directly on top of a PMOS transistor (or vice versa) within the footprint of a single gate. By eliminating the horizontal n-to-p boundary entirely, CFET enables a theoretical $50\%$ standard cell footprint reduction ($2\times$ transistor density increase), driving logic standard cell heights down from 5-track (5T) and 4.5T lateral nanosheets to ultra-dense 4-track (4T) and 3-track (3T) cells. Realizing this vertical 3D integration requires radical innovations across high-aspect-ratio superlattice epitaxy, self-aligned Middle Dielectric Isolation (MDI), dual-workfunction metal gate patterning, and Backside Power Delivery Networks (BSPDN).

Lateral GAA vs. Monolithic CFET Device Architecture elimination of the horizontal N-to-P boundary, vertical Middle Dielectric Isolation (MDI), and Backside Power Delivery LATERAL GAA (5T CELL HEIGHT ~120 nm) Bulk Silicon Substrate (STI Isolation) NMOS TIER N-Metal Gate W_ns = 35 nm DEAD SPACE S_NP ≈ 30 nm (40% of cell) PMOS TIER P-Metal Gate W_ns = 35 nm Total Lateral Cell Width ~ 135–150 nm Horizontal layout demands wide isolation and dual-STI trenches Severe area penalty limits scaling beyond 5T cells MONOLITHIC CFET (3T/4T CELL HEIGHT ~60–80 nm) TOP TIER: NMOS NANOSHEETS Al-TiC N-Workfunction Metal MIDDLE DIELECTRIC ISOLATION (MDI) t_MDI ≈ 15 nm BOTTOM TIER: PMOS NANOSHEETS TiN / W P-Workfunction Metal BACKSIDE POWER DELIVERY (BSPDN / BPR) Direct Through-Silicon Vias & Buried Power Rails 50% Cell Width Reduction (S_NP = 0)

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## 1. Physical Foundations: Overcoming the Lateral Scaling Wall

In modern CMOS logic scaling, the area of a standard logic cell (e.g., an inverter or 2-input NAND gate) is governed by the product of Contacted Poly Pitch (CPP) and Cell Height ($H_{cell}$):

$$A_{cell} = \text{CPP} \times H_{cell} = \text{CPP} \times (N_{tracks} \times \text{M2P})$$

Where $N_{tracks}$ is the cell track height (e.g., 6T, 5T, 4T) and $\text{M2P}$ is the contacted Metal-2 routing pitch ($20\text{ to }24\,\text{nm}$). In lateral configurations (FinFET and standard GAA nanosheet), cell height is constrained by:

$$H_{cell} = W_{NMOS} + W_{PMOS} + S_{NP} + 2 \cdot S_{boundary}$$

Where $W_{NMOS}$ and $W_{PMOS}$ are the active channel widths, $S_{boundary}$ is the cell boundary clearance, and $S_{NP}$ is the physical horizontal spacing between n-type and p-type active regions.

### 1.1 The $S_{NP}$ Scaling Bottleneck
To achieve low threshold voltages ($V_t$) and high carrier drive currents, NMOS and PMOS devices require distinct workfunction metal (WFM) gate stacks:
- NMOS WFM: Low workfunction metals (e.g., $\text{TiAl}$, $\text{TiAlC}$, $\Phi_m \approx 4.0\text{ to }4.2\,\text{eV}$) aligned near the silicon conduction band ($E_c$).
- PMOS WFM: High workfunction metals (e.g., $\text{TiN}$, $\text{TaN}$, $\Phi_m \approx 4.8\text{ to }5.2\,\text{eV}$) aligned near the silicon valence band ($E_v$).

In lateral devices, lithographic patterning and wet/dry etching of the NMOS workfunction metal must stop cleanly within the $S_{NP}$ space without encroaching upon the adjacent PMOS channel. At $S_{NP} < 20\,\text{nm}$, lithographic overlay error ($3\sigma \approx 2.5\,\text{nm}$) and chemical etchant capillary loading cause catastrophic cross-contamination, threshold voltage dispersion, and gate-to-source leakage. Consequently, $S_{NP}$ cannot scale below $\approx 22\,\text{nm}$, freezing lateral cell height scaling at 5 tracks ($H_{cell} \approx 110\text{ to }125\,\text{nm}$).

### 1.2 The CFET Solution: Vertical Folding
CFET eliminates the lateral $S_{NP}$ constraint by stacking the NMOS and PMOS devices vertically:

$$H_{cell,CFET} = \max(W_{NMOS}, W_{PMOS}) + 2 \cdot S_{boundary}$$

Because $S_{NP} \to 0$ in the horizontal plane, the standard cell height compresses from $5\text{T}\text{ (or }6\text{T})$ down to $4\text{T}\text{ or }3\text{T}$ ($H_{cell} \approx 60\text{ to }80\,\text{nm}$), achieving a dramatic $45\%\text{ to }55\%$ reduction in overall cell footprint without reducing individual nanosheet widths ($W_{ns}$).

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## 2. Quantitative Modeling: Standard Cell Scaling & Drive Current Density

CMOS Logic Evolution: Track Height & Standard Cell Area Scaling comparing FinFET, Lateral GAA, Forksheet, and Monolithic CFET across leading-edge nodes STANDARD CELL HEIGHT (nm) & TRACKS 240 nm 180 nm 120 nm 60 nm 0 210 nm 7.5T FinFET (7nm) 125 nm 5.0T GAA (3nm/2nm) 100 nm 4.3T Forksheet (A14) 66 nm 3.0T CFET (A10) Device Architecture Generation → INVERTER LOGIC CELL FOOTPRINT COMPARISON LATERAL GAA INVERTER (5T) Area: 0.0054 µm² NMOS S_NP PMOS Horizontal Dimension: 2 × CPP ≈ 90 nm | Height: 120 nm MONOLITHIC CFET INVERTER (3T) Area: 0.0026 µm² (-52%) TOP NMOS (W_ns = 35 nm) BOTTOM PMOS (W_ns = 35 nm) Zero N-to-P Dead Space | 2× Effective Current / Footprint

### 2.1 Effective Channel Width and Drive Current Formulation
In Gate-All-Around architectures, the total effective conduction width $W_{eff}$ of a nanosheet stack having $N_{sheets}$ sheets with nanosheet width $W_{ns}$ and nanosheet thickness $T_{ns}$ is:

$$W_{eff} = N_{sheets} \cdot (2 W_{ns} + 2 T_{ns})$$

For a typical nanosheet geometry ($N_{sheets} = 3$, $W_{ns} = 35\,\text{nm}$, $T_{ns} = 5\,\text{nm}$):

$$W_{eff} = 3 \cdot \big( (2 \cdot 35) + (2 \cdot 5) \big) = 3 \cdot (70 + 10) = 240\,\text{nm}$$

In lateral GAA, achieving this $W_{eff}$ for both NMOS and PMOS requires spanning a total horizontal layout width of:

$$W_{total,lateral} = W_{ns,N} + W_{ns,P} + S_{NP} + 2 \cdot S_{boundary} \approx 35 + 35 + 25 + 30 = 125\,\text{nm}$$

In CFET, because NMOS and PMOS share the same planar coordinate, the cell width contracts to:

$$W_{total,CFET} = \max(W_{ns,N}, W_{ns,P}) + 2 \cdot S_{boundary} \approx 35 + 30 = 65\,\text{nm}$$

The effective drive current density per unit of silicon footprint area ($J_{footprint}$) scales by more than $2.1\times$:

$$J_{footprint} = \frac{I_{on,NMOS} + I_{on,PMOS}}{A_{cell}}$$

Where $I_{on} = W_{eff} \cdot v_{sat} \cdot C_{ox} (V_{DD} - V_t)$. CFET provides the highest current-carrying capacity per unit area of any known solid-state device architecture.

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## 3. Manufacturing Architectures: Monolithic vs. Sequential CFET

Two competing process integration schemes exist for fabricating CFET devices:

+----------------------------------------------------------------------------------------------------+
|                               MONOLITHIC VS. SEQUENTIAL CFET INTEGRATION                           |
+----------------------+-------------------------------------+---------------------------------------+
| INTEGRATION METRIC   | MONOLITHIC CFET                     | SEQUENTIAL (3D COOLCUBE) CFET         |
+----------------------+-------------------------------------+---------------------------------------+
| Substrate Starting   | Single crystalline silicon wafer    | Two separate wafers; bottom tier fabbed|
| Material             | with multi-layer superlattice growth| then top thin layer fusion-bonded     |
+----------------------+-------------------------------------+---------------------------------------+
| Thermal Budget       | Shared high-temp budget             | Top tier restricted to <400°C to      |
| Constraints          | (Rapid thermal anneal at >950°C)    | prevent bottom tier silicide/dopant   |
|                      |                                     | deactivation                          |
+----------------------+-------------------------------------+---------------------------------------+
| Inter-Tier Alignment | Photolithographic self-alignment    | Bound by wafer-to-wafer bonding       |
| Accuracy             | (<1.0 nm via shared fin etch)       | overlay error (>5.0 to 10.0 nm)       |
+----------------------+-------------------------------------+---------------------------------------+
| Process Complexity   | Extreme aspect-ratio etching        | Low-temp gate dielectric & dopant     |
| Bottleneck           | (Aspect ratio > 20:1 for fins & MDI)| activation; wafer bonding yield       |
+----------------------+-------------------------------------+---------------------------------------+
| Channel Materials    | Homogeneous Si/SiGe superlattice    | Heterogeneous possible: Ge/InGaAs     |
| Flexibility          | (Limited bandgap engineering)       | PMOS on Silicon NMOS                  |
+----------------------+-------------------------------------+---------------------------------------+
| Industry Adoption    | Primary commercial roadmap          | Research roadmap for future           |
| Status               | (TSMC A14/A10, Intel 10A, Imec)     | heterogeneous multi-material logic    |
+----------------------+-------------------------------------+---------------------------------------+

### 3.1 Monolithic CFET Integration Flow
Monolithic CFET utilizes a continuous, single-wafer manufacturing flow based on ultra-tall epitaxial superlattices:
1. Multi-Tier Superlattice Epitaxy: Alternating thin layers of silicon and silicon-germanium ($\text{Si} / \text{Si}_{0.7}\text{Ge}_{0.3}$) are epitaxially grown on a bulk silicon substrate to define both tiers:
- Bottom tier: 3 nanosheet channels for PMOS.
- Middle sacrificial layer: 1 thick $\text{SiGe}$ layer ($t \approx 15\text{ to }20\,\text{nm}$) for Middle Dielectric Isolation (MDI).
- Top tier: 3 nanosheet channels for NMOS.
2. Tall Fin Etch: High-density plasma reactive ion etching (RIE) etches through the entire 8-to-10 layer stack, producing ultra-high aspect ratio fins ($\text{AR} > 20:1$) with strictly vertical sidewalls ($89.5^\circ\text{ to }90.0^\circ$).
3. Middle Dielectric Isolation (MDI): A crucial selective wet/vapor etch removes the middle thick $\text{SiGe}$ layer while leaving the nanosheets intact. Low-k dielectric ($\text{SiN}$ or $\text{SiCO}$) is deposited via Atomic Layer Deposition (ALD) and recessed to form the MDI dielectric barrier, physically isolating the top NMOS gate from the bottom PMOS gate.
4. Differential Source/Drain Epitaxy: The top NMOS source/drain regions ($\text{Si:P}$) are grown epitaxially, followed by dielectric encapsulation, allowing subsequent selective growth of bottom PMOS source/drain regions ($\text{SiGe:B}$).

### 3.2 Middle Dielectric Isolation (MDI) Electrical Physics
The MDI layer serves as the critical electrostatic barrier separating the NMOS and PMOS gate electrodes. The electric field $E_{MDI}$ across this layer must not exceed the dielectric breakdown field $E_{bd}$:

$$E_{MDI} = \frac{|V_{G,NMOS} - V_{G,PMOS}|}{t_{MDI}} < E_{bd} \approx 8\text{ to }10\,\text{MV/cm}$$

Under maximum opposing bias conditions ($V_{G,NMOS} = V_{DD} \approx 0.8\,\text{V}$, $V_{G,PMOS} = 0\,\text{V}$), an MDI thickness of $t_{MDI} = 15\,\text{nm}$ yields:

$$E_{MDI} = \frac{0.8\,\text{V}}{15 \times 10^{-7}\,\text{cm}} \approx 0.53\,\text{MV/cm} \ll E_{bd}$$

This ensures zero gate-to-gate leakage and eliminates parasitic turn-on of the unselected vertical channel.

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## 4. Backside Power Delivery Network (BSPDN) Co-Integration

CFET cannot achieve its theoretical scaling potential without Backside Power Delivery Networks (BSPDN). In conventional front-side power grids, power rails ($V_{DD}$ and $V_{SS}$) compete directly with signal interconnects for routing tracks in the lower metal layers (M0, M1, M2).

In a 3T or 4T CFET cell, there are only 3 or 4 available metal routing tracks per cell height. Allocating two tracks to power delivery leaves only 1 or 2 tracks for signal routing, causing catastrophic pin inaccessibility and routing congestion.

+----------------------------------------------------------------------------------------------------+
|                                    CFET + BSPDN CO-DESIGN ARCHITECTURE                             |
+----------------------------------------------------------------------------------------------------+
|  [ FRONT-SIDE BEOL ]  ==> Metal 1 to Metal 15 (Dedicated 100% to Signal Routing & Clock Trees)     |
|  ------------------------------------------------------------------------------------------------  |
|  [ TOP TIER ]         ==> NMOS Nanosheets (Drain/Source connected to Front-Side M0 Contacts)       |
|  [ MDI BARRIER ]      ==> Middle Dielectric Isolation Layer (t_MDI = 15 nm)                        |
|  [ BOTTOM TIER ]      ==> PMOS Nanosheets (Drain connected to Front, Source to Backside)           |
|  ------------------------------------------------------------------------------------------------  |
|  [ BURIED POWER RAILS]==> Tungsten/Ruthenium Buried Power Rails (BPR) embedded in STI              |
|  [ BACKSIDE TSVs ]    ==> Nano-TSVs (Pitch < 100 nm, Height < 200 nm) contacting BPR              |
|  [ BACKSIDE BEOL ]    ==> Thick Copper Backside Metal Layers (BM0–BM3) carrying V_DD & V_SS        |
+----------------------------------------------------------------------------------------------------+

Co-integrating BSPDN with CFET yields two decisive advantages:
1. $100\%$ Signal Routing Track Availability: All front-side tracks (M0–M3) are reserved for intra-cell and inter-cell logic connections, resolving routing DRC violations in 3T cells.
2. $40\%$ IR Drop Reduction: Routing power through wide, thick copper lines on the wafer backside reduces power distribution network (PDN) impedance, slashing dynamic supply voltage droop ($V_{droop} = L \frac{dI}{dt} + I R$) and enabling stable sub-0.7 V operation.

---

## 5. Technology Comparison: Multi-Generation Logic Roadmap

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF LOGIC ARCHITECTURES                            |
+----------------------+---------------------+-----------------------+-------------------------------+
| METRIC               | FINFET (N5/N3)      | LATERAL GAA (N2/A16)  | MONOLITHIC CFET (A14/A10)     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Device Channel Form  | Vertical 3D Fin     | 3–4 Stacked Nanosheets| Vertically Stacked N-over-P   |
|                      | (3-sided gate)      | (4-sided gate-all-around) Nanosheet Pairs             |
+----------------------+---------------------+-----------------------+-------------------------------+
| Standard Cell Height | 6.0T to 7.5T        | 4.5T to 5.0T          | 3.0T to 4.0T                  |
| Track Count          | (~135 nm to 180 nm) | (~100 nm to 125 nm)   | (~60 nm to 80 nm)             |
+----------------------+---------------------+-----------------------+-------------------------------+
| N-to-P Boundary Dead | Wide (25 to 40 nm)  | Moderate (20 to 30 nm)| Zero Horizontal Space         |
| Space Penalty        | (35–45% cell area)  | (30–40% cell area)    | (N-over-P vertical stacking)  |
+----------------------+---------------------+-----------------------+-------------------------------+
| Relative Logic Gate  | 1.0× (Baseline)     | ~1.4× to 1.6×         | ~2.8× to 3.2×                 |
| Density              |                     |                       |                               |
+----------------------+---------------------+-----------------------+-------------------------------+
| Power Delivery       | Front-side BEOL     | Front-side or BSPDN   | Mandatory Backside Power      |
| Architecture         |                     | (Intel PowerVia, A16) | Delivery (BSPDN + BPR)        |
+----------------------+---------------------+-----------------------+-------------------------------+
| Electrostatic Gate   | Moderate (DIBL      | Superior (DIBL        | Superior (DIBL < 40 mV/V,     |
| Control              | ~65 mV/V)           | ~45 mV/V)             | Subthreshold Swing ~65 mV/dec)|
+----------------------+---------------------+-----------------------+-------------------------------+
| Manufacturing Aspect | Low to Moderate     | High (Epi superlattice| Extreme (>20:1 Fin Etch, MDI  |
| Ratio Challenge      | (Aspect ratio ~8:1) | release etch ~12:1)   | formation, dual-metal gate)   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Production Horizon   | High-Volume Mature  | Initial Production    | R&D / Pilot Production Target |
|                      | (2020–2024)         | (2025–2027)           | (2028–2030+)                  |
+----------------------+---------------------+-----------------------+-------------------------------+

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