control plan
**Control plan** is a **comprehensive document that specifies all quality controls, inspection methods, and reaction plans for every process step in semiconductor manufacturing** — serving as the master recipe for how product quality is monitored, maintained, and protected from wafer start through final test and shipment.
**What Is a Control Plan?**
- **Definition**: A living document that lists every process parameter to be controlled, the control method, measurement technique, sampling frequency, specification limits, and reaction plan for out-of-specification conditions.
- **Standard**: Required by IATF 16949 (automotive), AS9100 (aerospace), and widely used in semiconductor manufacturing as a quality management best practice.
- **Scope**: Covers the entire manufacturing flow — incoming material inspection, each fab process step, assembly, packaging, final test, and outgoing quality.
**Why Control Plans Matter**
- **Consistency**: Ensures every shift, every operator, and every tool applies the same quality controls — preventing variation in how quality is monitored.
- **Reaction Speed**: Pre-defined reaction plans enable immediate, consistent response to out-of-control conditions — no waiting for engineering decisions.
- **Customer Requirement**: Major semiconductor customers (automotive OEMs, Apple, Qualcomm) require documented control plans as a qualification prerequisite.
- **Audit Trail**: Provides objective evidence for quality auditors that all critical parameters are controlled throughout manufacturing.
**Control Plan Elements**
- **Process Step**: Each manufacturing operation (CVD, etch, litho, CMP, implant, test, etc.).
- **Product/Process Characteristic**: The specific parameter being controlled (film thickness, CD, overlay, particle count, etc.).
- **Specification/Tolerance**: The acceptable range for each characteristic — with LSL (Lower Spec Limit) and USL (Upper Spec Limit).
- **Measurement Method**: The tool and technique used to measure each characteristic — ellipsometry, SEM, scatterometry, electrical test, etc.
- **Sampling Plan**: How many wafers/sites measured and how often — every wafer, lot sampling, or periodic monitoring.
- **Control Method**: SPC charts, automated FDC monitoring, 100% inspection, or periodic audit.
- **Reaction Plan**: Specific steps to take when a parameter goes out of control — stop production, quarantine, reinspect, containment, engineering review.
**Control Plan Phases**
| Phase | When Used | Detail Level |
|-------|-----------|-------------|
| Prototype | During development | Initial controls for first silicon |
| Pre-Launch | During qualification | Enhanced monitoring, tighter sampling |
| Production | Volume manufacturing | Optimized controls based on data |
Control plans are **the operational backbone of semiconductor quality management** — translating process knowledge and customer requirements into specific, actionable controls that protect product quality at every step from wafer start to customer delivery.