copper electromigration reliability

**Copper Electromigration (EM) Reliability** is the **failure mechanism where sustained electrical current through copper interconnect wires gradually displaces metal atoms via momentum transfer from conducting electrons — creating voids where atoms are depleted and hillocks where they accumulate, eventually causing open-circuit failures that limit the operational lifetime of semiconductor products, governed by Black's equation (MTTF ∝ J⁻ⁿ × e^(Ea/kT)) where current density and temperature are the dominant accelerating factors**. **The Physics of Electromigration** At current densities >10⁵ A/cm² (typical for local interconnects), the "electron wind" — momentum transferred from conduction electrons to copper atoms — exerts a force on the metal lattice. Copper atoms preferentially migrate along grain boundaries and the interface between copper and the barrier/cap layers. Over time: - **Void Formation**: Atoms migrate away from cathode-end of a via or grain boundary triple point, creating a void. The void grows until it spans the wire cross-section → open circuit. - **Hillock Formation**: Atoms accumulate at the anode end, forming hillocks that can extrude through the cap layer and short to adjacent wires. **Black's Equation** MTTF = A × J⁻ⁿ × exp(Ea / kT) - **J**: Current density (A/cm²). Higher current → faster failure. n ≈ 1-2 for copper (n=1 for void nucleation-limited, n=2 for void growth-limited). - **Ea**: Activation energy for the dominant diffusion path. Cu/cap interface: 0.7-1.0 eV. Grain boundary: 0.7-0.9 eV. Bulk: 2.1 eV. The lowest-Ea path dominates reliability. - **T**: Temperature. Every 10-15°C increase roughly halves the EM lifetime. **EM-Aware Design Rules** Foundries specify maximum allowed current density for each wire width, via type, and metal layer — typically 1-5 mA/μm for long-lines at 105°C junction temperature. EDA tools (Cadence Voltus, Synopsys ICC) check every wire and via in the design against these limits, flagging EM violations that require wider wires, parallel paths, or additional vias. **Improving EM Lifetime** - **Redundant Vias**: Two or more vias instead of one at each connection. If one via fails, current re-routes through the redundant via. Standard design practice that improves effective lifetime by 10-100x. - **Metal Cap (CoWP, CuMn)**: Replacing the SiCN dielectric cap with a metallic cap (electroless CoWP or CuMn alloy self-forming barrier) on top of copper changes the dominant diffusion path from the weak Cu/dielectric interface to the much stronger Cu/metal interface, improving Ea by 0.2-0.3 eV and extending lifetime by 10-100x. - **Bamboo Structure**: When the wire width is narrower than the average grain size, the grain boundary structure forms "bamboo" segments with no continuous grain boundary path for diffusion. This shifts the diffusion path from fast grain boundary to slow lattice, dramatically improving EM lifetime — one reason why narrow wires at advanced nodes can have better EM than wider wires. Copper Electromigration is **the slow death sentence that every interconnect wire carries** — a physics-driven clock where current density and temperature determine how many years a wire will function before the cumulative drift of atoms creates a void large enough to break the circuit.