copper interconnect
**Copper interconnect** is the on-chip wiring system that connects billions of transistors through a multi-layer metal stack — 10–15 layers of copper lines and vias fabricated by dual-damascene processing, separated by low-k dielectrics, and capped by diffusion barriers. Copper replaced aluminum at the 180 nm node (IBM, 1997) because its ~40% lower bulk resistivity (1.7 µΩ·cm vs 2.7 µΩ·cm for Al) directly translates to lower RC delay and higher current-carrying capacity. The CFS Interconnect Simulator at /interconnect models the full RC delay and electromigration lifetime of these copper wires.
**Dual-damascene process — how copper lines are made.** Unlike aluminum (deposited and then etched), copper cannot be plasma-etched without redepositing non-volatile byproducts. The industry therefore uses the damascene (inlaid) process:
1. **Trench/via patterning.** Etch trenches (for lines) and vias (for vertical connections) into the low-k ILD using photoresist masks.
2. **Barrier deposition.** Deposit a thin (2–5 nm) TaN adhesion/barrier layer plus a Ta or Co wetting layer by PVD — this prevents copper from diffusing into the dielectric (Cu is a fast diffuser in SiO₂ and poisons transistors at ppm levels).
3. **Copper seed.** PVD a thin Cu seed (~30–50 nm) on the barrier to enable electroplating.
4. **Electrochemical deposition (ECD).** Electroplate copper from a CuSO₄ bath to fill the trenches and vias bottom-up without voids (superfilling enabled by accelerator/suppressor/leveler additives).
5. **CMP.** Chemically-mechanically polish away the overburden copper, stopping on the barrier/ILD surface — leaving copper only in the damascene features.
6. **Cap.** Deposit a dielectric cap (SiCN or selective metal cap) over the polished surface to seal the copper and provide the etch-stop for the next layer.
This sequence repeats for each metal layer, building the stack from M1 (finest pitch, closest to transistors) up through global routing layers (thickest, widest).
**The size-effect crisis — resistivity at nanoscale.** Bulk copper has $\rho$ = 1.7 µΩ·cm, but at line widths below ~40 nm, resistivity rises steeply due to:
$$\rho_{\text{eff}} = \rho_{\text{bulk}} \cdot \Bigl(1 + \frac{3\lambda}{8w}(1-p) + \frac{3\lambda}{4d} \cdot \frac{R}{1-R}\Bigr)$$
This is the **Fuchs–Sondheimer** (surface scattering) + **Mayadas–Shatzkes** (grain-boundary scattering) model, where $\lambda$ is the electron mean free path (~39 nm for Cu at room temperature), $w$ is line width, $d$ is grain size, $p$ is the surface specularity parameter (0 = fully diffuse), and $R$ is the grain-boundary reflection coefficient.
| Line width (nm) | $\rho_{\text{eff}}$ Cu (µΩ·cm) | Multiplier vs bulk | Node | Impact |
|---|---|---|---|---|
| 100 | 2.2 | 1.3× | 45 nm | Manageable |
| 50 | 3.0 | 1.8× | 14 nm | Noticeable RC increase |
| 28 | 4.5–5.5 | 2.6–3.2× | 5 nm | Significant — RC dominates delay |
| 20 | 6–8 | 3.5–4.7× | 3 nm | Severe — alternative metals considered |
| 14 | 8–12 | 4.7–7× | 2 nm | At parity with Co/Ru at this width |
At sub-20 nm widths, the mean free path (39 nm) exceeds the wire dimension — electrons scatter off surfaces and grain boundaries more often than off phonons, and resistivity can triple or quadruple. This is why the BEOL RC delay — not the transistor — is the dominant performance limiter at 3 nm and below.
**Alternative metals — beyond copper.** At the finest pitches (M0/M1 at 2 nm node, width ~10–14 nm), several metals are being evaluated to replace or supplement copper:
| Metal | Bulk $\rho$ (µΩ·cm) | Mean free path (nm) | Advantage at <20 nm | Status |
|---|---|---|---|---|
| Cu | 1.7 | 39 | Lowest bulk $\rho$, but MFP too long → severe size effect | Incumbent, all nodes |
| Co (cobalt) | 5.6 | 12 | Short MFP → less size effect; barrierless (self-barrier) | M0/M1 at Intel 10nm+, TSMC N5 local |
| Ru (ruthenium) | 7.1 | 6.5 | Very short MFP → flat $\rho$ at narrow widths; barrierless | In development for sub-14 nm lines |
| Mo (molybdenum) | 5.3 | 14 | Good fill properties, no barrier needed | Research stage |
| W (tungsten) | 5.3 | 15 | Already used for contacts/vias; high melting point | Local interconnect, via fill |
The crossover: below ~12–14 nm line width, cobalt and ruthenium (despite 3–4× higher bulk $\rho$) have lower effective resistivity than copper because they don't need a barrier (which steals cross-sectional area) and their short MFP means less size-effect blow-up.
**The barrier problem.** A 2–3 nm TaN/Ta barrier on each side of a 20 nm trench consumes 20–30% of the total cross-sectional area — leaving only 14–16 nm of actual copper. This "liner penalty" becomes the dominant resistance contributor at fine pitches. Solutions: (1) thinner barriers via ALD (sub-1 nm TaN); (2) barrierless metals (Co, Ru) that don't diffuse into SiO₂; (3) SAM (self-assembled monolayer) barriers that occupy <1 nm.
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**Reliability — electromigration in copper.** Current density in the finest metal layers can exceed 1–2 MA/cm² — high enough that the electron wind pushes Cu atoms along the Cu/cap interface, forming voids (see the CFS electromigration keyword). The barrier adhesion, cap material (SiCN vs CoWP vs Ru cap), and grain structure (large bamboo grains are better than small polycrystalline grains) determine the EM lifetime. Design rules limit current per wire and per via, and redundant vias are used to survive single-via voiding.
**What copper interconnect means for AI chips.** A modern GPU at 5 nm has >100 km of total wire length across 13+ metal layers, carrying the data between tensor cores, caches, and memory controllers. The interconnect — not the transistors — often limits maximum frequency at advanced nodes because BEOL RC delay grows as pitches shrink (resistivity rises from size effects while capacitance stays roughly constant). Every node's "performance gain" is partly enabled by improvements in the copper metallization process — liner thinning, grain optimization, and the eventual transition to cobalt/ruthenium at the finest layers.