copper seed layer
**Copper Seed Layer for Electroplating** is the **thin conductive film deposited by physical vapor deposition (PVD) that serves as the starting surface for electrolytic copper electroplating of interconnect trenches and vias** — since electroplating requires an electrically continuous conductive substrate, the PVD seed layer provides the starting current path while the underlying barrier layer (TaN/Ta or Ru) prevents copper diffusion into silicon and dielectrics, with seed continuity at the bottom and sidewalls of narrow features being among the most challenging requirements in back-end-of-line metallization.
**Interconnect Fill Stack**
```
Cu fill (electroplated) ← Fills trench/via
Cu seed (PVD, 3–10 nm) ← Conductive starting surface
Ta barrier (PVD, 2–5 nm) ← Diffusion barrier (if Ta used)
TaN barrier (PVD, 2–5 nm) ← Adhesion + barrier
Low-k dielectric ← Surrounding dielectric
Silicon or lower metal ← Substrate
```
**Seed Layer Requirements**
- Continuous film: Must cover entire trench sidewall and bottom → no gaps → pinhole = void in electroplated Cu.
- Thick enough for current distribution: Seed must carry plating current uniformly → 3–10 nm minimum.
- Thin enough for gap fill: Thick seed in narrow trench → constricts via → reduces plating space → void formation.
- Adhesion: Must adhere to barrier layer → prevent delamination during CMP and thermal cycling.
**PVD (Sputter) Deposition Challenges**
- PVD is line-of-sight: Atoms arrive from source → shadow effects at high-AR sidewalls → thin coverage at bottom.
- Aspect ratio limit: Conventional PVD → poor coverage at AR > 3:1 → sputtered atoms cannot reach bottom.
- Ionized PVD (iPVD / IMPVD): RF coil ionizes sputtered atoms → ions directed by bias toward substrate → improved bottom coverage at AR 5–10:1.
**Ru Seed / Ru Barrier-Seed (Advanced Nodes)**
- At < 20nm line width: Ta/TaN barrier too thick → consumes too much of via volume → resistance increase.
- Ruthenium (Ru): Very thin barrier + seed in one layer → Ru can be 1–2 nm vs Ta/TaN at 4–7 nm.
- Ru nucleation: Cu deposits conformally on Ru even at very thin Ru → excellent seed for Cu plating.
- Ru CVD/ALD: Conformal Ru deposition → covers high-AR features without PVD shadow issue.
- Ru used at 5nm node by TSMC and Intel for critical inner metal layers.
**Void Formation Mechanisms**
- **Pinhole in seed**: Breaks current path → no plating at pinhole → void in plated Cu.
- **Overhang**: Thick seed at trench opening → necks down → fills top before bottom → seam void.
- **Aspect ratio too high**: Seed thin at bottom → current concentrates at top → fills top-down → unfilled bottom.
**Electroless vs Electrolytic Seeding**
- Electrolytic (standard): Requires current → seed must be pre-deposited.
- Electroless copper: Chemical reduction → no current path needed → can plate without seed.
- Issue: Electroless bath difficult to control → not widely used in production for main fill.
- Used for: Specific applications (through-glass vias, advanced packaging).
**Seed CMP and Overburden**
- After plating: Cu overburden + seed + barrier must be planarized by CMP.
- CMP removes bulk Cu → stops on barrier layer → clears barrier on field → stops on low-k dielectric.
- Seed etch back: Before plating, thinning seed in field (not in trench) prevents excessive overburden → faster CMP.
Copper seed layer deposition is **the enabling step that bridges the barrier layer with the electroplated bulk copper** — as interconnect dimensions shrink below 20nm, the requirement to continuously coat 1–2 nm of Ru on near-vertical sidewalls 10–15nm wide and 50nm deep using ALD or highly ionized PVD represents one of the most demanding thin-film deposition challenges in semiconductor manufacturing, where a single nanometer of coating non-uniformity directly translates to either void formation (missing seed) or resistance increase (too-thick seed consuming via volume), making seed layer process control a first-order determinant of interconnect resistance and yield at leading nodes.