cryogenic etch
**Cryogenic Etching** is the **plasma etch technique performed at extremely low wafer temperatures (-80°C to -120°C) where condensation of passivating species on sidewalls enables highly anisotropic deep silicon etching without the cyclic roughness of Bosch process** — producing smooth, vertical sidewalls in a single continuous step, essential for MEMS fabrication, through-silicon vias (TSVs), photonic devices, and advanced 3D integration where sidewall quality directly impacts device performance.
**Cryogenic vs. Bosch Process**
| Feature | Bosch (DRIE) | Cryogenic |
|---------|-------------|----------|
| Mechanism | Cyclic: etch (SF₆) / passivate (C₄F₈) | Continuous: etch + passivate simultaneously |
| Temperature | Room temperature (20°C) | -80 to -120°C |
| Sidewall profile | Scalloped (cyclic roughness) | Smooth (no scalloping) |
| Etch rate | 5-20 µm/min | 3-10 µm/min |
| Aspect ratio | >50:1 | >30:1 |
| Selectivity (Si:resist) | 50-200:1 | 100-300:1 |
| Gas system | SF₆ + C₄F₈ (alternating) | SF₆ + O₂ (continuous) |
**How Cryogenic Etch Works**
- Gas: SF₆ (etchant) + O₂ (passivation source) simultaneously.
- At -100°C: SiOₓFᵧ passivation layer condenses on cold sidewalls.
- Bottom of feature: Ion bombardment sputters away passivation → etching continues downward.
- Sidewalls: No ion bombardment → passivation remains → blocks lateral etch.
- Result: Anisotropic etch with smooth sidewalls in single continuous process.
**Temperature-Dependent Behavior**
- Too warm (>-60°C): Passivation does not condense → isotropic etch (undercut).
- Optimal (-90 to -110°C): Passivation condenses on sidewalls but not on bombarded bottom.
- Too cold (<-130°C): Passivation too stable → etch rate drops, grass/micromasking appears.
- Narrow process window: ±10°C affects profile significantly → precise chuck cooling required.
**Applications**
| Application | Depth | Feature Size | Why Cryo |
|------------|-------|-------------|----------|
| MEMS resonators | 10-50 µm | 1-10 µm | Smooth sidewalls for Q-factor |
| TSV formation | 50-100 µm | 5-10 µm | No scallops for reliable fill |
| Photonic waveguides | 1-5 µm | 0.3-1 µm | Smooth walls for low optical loss |
| Micro-lens arrays | 5-20 µm | 10-50 µm | Controlled profile shape |
| Quantum device fabrication | 0.1-1 µm | 50-200nm | Ultra-smooth, low damage |
**Process Challenges**
| Challenge | Cause | Solution |
|-----------|-------|----------|
| Photoresist cracking | Thermal stress at cryo temp | Use hard mask (SiO₂, metal) |
| Black silicon/grass | Micro-masking at low temp | Optimize O₂ flow, avoid contamination |
| Loading effect | Non-uniform etch across pattern densities | Tune pressure and gas ratio |
| Wafer clamping | Thermal contact at -100°C | He backside cooling, electrostatic chuck |
| Passivation removal | Residual SiOₓFᵧ after etch | Warm wafer to RT → passivation desorbs |
**Advanced: Cryo-ALE**
- Cryogenic atomic layer etch: Combine cryo temperature with self-limiting ALE cycles.
- Enables sub-nm per-cycle removal with perfect anisotropy.
- Emerging application: Gate etch, spacer etch at most advanced nodes.
Cryogenic etching is **the process technology that delivers the smoothest deep silicon structures in semiconductor manufacturing** — by leveraging temperature-dependent passivation physics rather than cyclic chemistry switching, cryogenic etch eliminates the scalloping inherent to Bosch processing, enabling mirror-smooth sidewalls that are critical for optical, MEMS, and quantum devices where nanometer-scale surface roughness directly degrades performance.