design closure
**Design Closure** is the **iterative process of simultaneously satisfying all physical design constraints** — timing, power, area, DRC, LVS, and signal integrity — to reach a tapeout-ready implementation.
**What Closure Means**
- **Timing closure**: WNS ≥ 0, TNS = 0 at all required PVT corners and modes.
- **Power closure**: Total chip power within package TDP and per-rail current limits.
- **Area closure**: Total die area within reticle budget and cost targets.
- **Physical closure**: DRC = 0 violations, LVS = clean, antenna = clean.
- **SI (Signal Integrity) closure**: Crosstalk, IR drop, and EM within limits.
**The Closure Challenge**
- Each constraint competes with others:
- Improving timing → upsize cells → more area + more power.
- Fixing IR drop → widen power rails → less routing resource → more congestion → timing fails.
- Adding decap → area increases → less room for standard cells → utilization worsens.
- Closure is fundamentally an optimization problem over conflicting constraints.
**Closure-Driven Physical Design Flow**
```
Floorplan → Placement → CTS → Route → Signoff
↑_____________feedback ECOs____________|
```
- Typical convergence: 5–20 iterations of place/route/signoff for advanced designs.
- Each iteration incorporates fixes from previous signoff analysis.
**Closure Bottlenecks by Technology Node**
| Node | Primary Closure Bottleneck |
|------|---------------------------|
| 28nm | Timing, congestion |
| 16/14nm FinFET | Timing, density rules |
| 7nm | Routing congestion, OCV pessimism |
| 5nm | DRC complexity, timing with OCV, power |
| 3nm GAAFET | All simultaneously, new DRC rules |
**Sign-Off Checklist**
- STA sign-off: PrimeTime or Tempus at all corners.
- Power sign-off: PrimePower, Voltus.
- Physical sign-off: Calibre DRC, LVS.
- Reliability: EM/IR sign-off.
- Formal verification: Equivalence check post-ECO.
Design closure is **the ultimate test of the entire design team's capabilities** — integrating hundreds of person-months of work into a manufacturable, functioning, spec-compliant chip at the required performance, power, and cost points is the defining challenge of modern physical design.