design technology co optimization dtco

**Design-Technology Co-Optimization (DTCO)** is the **methodology where semiconductor process technology and circuit/physical design are developed jointly and iteratively — rather than sequentially (process first, design rules second) — to achieve optimal combinations of transistor performance, interconnect density, and cell area that neither discipline could achieve independently, representing the primary mechanism for continued scaling at nodes where pure transistor or pure interconnect improvements alone yield diminishing returns**. **Why DTCO Is Now Essential** Historically, foundries developed a process technology, published design rules, and designers used those rules. At 28 nm and above, process scaling alone delivered sufficient improvement. At 7 nm and below, the interactions between process capability and design architecture are so tightly coupled that process decisions and design decisions must be made simultaneously: - A 10% tighter metal pitch might enable 5% smaller cells but requires process development investment. - A different cell architecture (fewer fins, buried power rail) might relax metal pitch requirements while achieving the same density. DTCO finds the Pareto-optimal combinations. **Key DTCO Knobs** - **Cell Height (Track Height)**: Standard cells are measured in metal pitch tracks. Reducing from 7.5-track (7 nm) to 6-track (5 nm) to 5-track (3 nm) dramatically increases gate density. But fewer tracks means fewer routing resources — requiring tighter metal pitch or more metal layers. - **Contacted Poly Pitch (CPP)**: The distance between adjacent transistor gates. Smaller CPP = higher logic density but requires tighter lithography and contact-over-active-gate (COAG) to maintain routing access. - **Fin/Nanosheet Count**: Reducing from 3-fin to 2-fin devices reduces cell width. But fewer fins means lower drive current — process must compensate with higher mobility (strain) or lower threshold voltage. - **Buried Power Rail (BPR)**: Moving power rails below the transistor level into the substrate (or backside) eliminates power rail area from the standard cell, enabling smaller cell height without losing signal routing. - **Self-Aligned Features**: Self-aligned gate contact (SAGC), self-aligned via, and COAG enable denser feature placement by using process alignment rather than lithographic overlay. **DTCO Flow** 1. **Define Performance/Density Targets**: Target PPA (Performance, Power, Area) metrics for the node. 2. **Enumerate Design Architecture Options**: Cell heights (5T, 5.5T, 6T), fin/nanosheet counts, BPR options, CPP choices. 3. **Process Feasibility Assessment**: For each design option, evaluate required process capabilities (metal pitch, overlay, etch selectivity). 4. **Circuit-Level Evaluation**: Simulate representative circuits (ARM cores, SRAM, standard cell libraries) under each design-process combination. 5. **Iterate**: Refine process targets and design architecture based on circuit results. Converge on the optimal combination. **DTCO Results at Recent Nodes** | Node | Cell Height | CPP | Metal Pitch (M1) | Key DTCO Innovation | |------|------------|-----|------------------|---------------------| | 7 nm | 7.5T | 54 nm | 36 nm | EUV single patterning | | 5 nm | 6T | 48 nm | 28 nm | EUV multi-layer | | 3 nm | 5T | 45 nm | 24 nm | COAG, single-fin option | | 2 nm (GAA) | ~5T | 42 nm | 20-22 nm | BPR, BSPDN, nanosheet | DTCO is **the collaborative methodology that extracts maximum scaling benefit from each technology generation** — recognizing that the era of independent process and design optimization is over, and that the future of semiconductor scaling lies in the synergistic co-design of transistors, interconnects, and circuit architectures.