Devices

A semiconductor device is a structure that exploits the controllable conductivity of a semiconductor to do one useful job: switch, amplify, rectify, store charge, or convert between light and current. A modern chip is not a menagerie of these — it is a handful of device types repeated billions of times, and almost all of the interesting engineering is in how well one of them, the MOSFET, can be made to turn off.

Almost everything on a logic die is one device repeated. A processor with a hundred billion transistors has essentially two kinds of them: n-channel and p-channel MOSFETs, wired as complementary pairs so that a static CMOS gate draws current only while it switches. Resistors, capacitors and diodes exist on the die, but mostly as parasitics to be minimised rather than components to be placed. When a foundry talks about a node, it is talking about what it can do to that one switch.

The switch is judged on four numbers, and they fight each other. Drive current Ion sets how fast a gate can charge the next one. Off-state leakage Ioff sets how much power the chip burns doing nothing. Gate capacitance sets how much charge each switching event costs. And subthreshold swing — millivolts of gate voltage per decade of current — sets how quickly the device can get from off to on. Improve one by brute force and you lose another.

Subthreshold swing has a floor that no geometry can beat. Carriers crossing the channel barrier follow Boltzmann statistics, so the current below threshold falls by a factor of ten for every (kT/q)·ln 10 of gate voltage. At 300 K, kT/q is 25.9 mV, which puts the floor at 59.6 mV per decade — call it 60. Production FinFET and nanosheet devices land around 65–70 mV/dec, close to the limit and unable to pass it. This is why supply voltage stopped falling: at roughly 0.7 V there is no longer enough gate swing to put five or six decades between off and on. Dennard scaling ended here, not at any lithographic wall.

Geometry changed because the gate was losing the argument. In a long channel the gate is the only thing with a say over whether current flows. As the channel shortens, the drain starts to influence the barrier directly — short-channel effects — and the device leaks no matter what the gate does. Every architecture change since 2011 has been a way of getting more gate surface around the channel: planar to FinFET at 22 nm, FinFET to gate-all-around nanosheets at 3 nm and 2 nm, and CFET next, which stacks the n-device on top of the p-device to halve the footprint of a logic cell.

Memory devices make the same trades with different priorities. A DRAM cell is one transistor and one capacitor; the transistor's job is to leak as little as possible, because the capacitor must hold its charge until the next refresh, and the capacitor itself is now a trench with an aspect ratio beyond 50:1 simply to keep enough farads in a shrinking footprint. An SRAM cell is six transistors in a latch — fast and leaky and large, which is why cache is expensive. A 3D NAND cell traps charge in a nitride layer and is stacked vertically, past 200 layers, accepting slow writes and limited endurance to win on cost per bit.

Power and RF devices are a different species entirely. Logic devices run current sideways in a film a few nanometres thick; a power device runs it vertically through the whole wafer, and is judged on breakdown voltage and on-resistance rather than switching speed. An IGBT covers 600 V to 6.5 kV in traction and grid hardware. A SiC MOSFET does 650 V to 1.7 kV with far lower switching loss, which is why it took over EV traction inverters. A GaN HEMT carries current in a two-dimensional electron gas formed at an AlGaN/GaN interface with no doping at all, and owns high-frequency power conversion.

Steep-slope devices are the standing attempt to break 60 mV/dec. A tunnel FET replaces thermal emission over the barrier with band-to-band tunnelling through it, which is not bound by Boltzmann statistics and has demonstrated sub-60 mV/dec swing in the laboratory. A negative-capacitance FET puts a ferroelectric such as doped HfZrO in the gate stack to amplify the surface potential internally. Neither has reached production: TFETs deliver too little on-current to be useful in logic, and NCFET stability and hysteresis remain unresolved. Treat any claim that either is imminent with scepticism.

Here is where the families sit relative to one another:

A node number tells you less about the device than the layout rules do. The label on a process — 3 nm, 2 nm — has not described a physical gate length for over a decade; physical gate lengths at those nodes sit nearer 16–18 nm. What actually distinguishes them is contacted poly pitch, metal pitch, how many fins or sheets a standard cell gets, and whether power arrives from the back of the wafer. Read a process by its cell architecture, not its marketing name.

Read devices through a *figures-of-merit* lens rather than a *device-zoo* lens: logic, memory, power and RF parts look unrelated, but each is the same bargain struck at a different point — how much current you can push while off, how steeply you can turn on, how much charge each switch costs, and how much voltage the structure survives. Once a device family is fixed, almost everything else about a chip built from it follows.