die per wafer (dpw)

Die Per Wafer is the **number of complete chip dies that fit on one wafer** based on the die size and wafer diameter. DPW directly determines the manufacturing cost per chip. **DPW Formula** A common approximation: DPW ≈ (π × (d/2)² / A) - (π × d / √(2A)) Where **d** = wafer diameter (300mm), **A** = die area (mm²). The first term is the total area divided by die size; the second term subtracts edge dies lost to the wafer's circular shape. **DPW Examples (300mm wafer)** • **Small die** (50 mm², e.g., simple MCU): ~1,200 dies • **Medium die** (100 mm², e.g., mobile SoC): ~640 dies • **Large die** (200 mm², e.g., laptop CPU): ~340 dies • **Very large die** (400 mm², e.g., server GPU): ~170 dies • **Massive die** (800 mm², e.g., NVIDIA H100): ~80 dies **Why DPW Matters** **Cost per die** = wafer cost / (DPW × die yield). A $16,000 wafer with 640 dies at 90% yield = **$28 per die**. The same wafer with 80 dies at 80% yield = **$250 per die**. This is why large AI chips are expensive—fewer dies per wafer combined with lower yield dramatically increases cost. **Maximizing DPW** **Smaller die design**: Use chiplets instead of monolithic dies to keep individual chiplet sizes small. **Die shape optimization**: Rectangular dies that tile efficiently waste less wafer edge area. **Wafer edge utilization**: Some partial-edge dies may be usable depending on circuit layout. **Larger wafers**: Moving from 200mm to 300mm wafers increased usable area by **2.25×**, dramatically improving DPW for all die sizes. **The Chiplet Strategy** AMD's EPYC processors use multiple small chiplets (~72 mm² each) instead of one large die. This dramatically increases DPW and yield compared to a monolithic design, reducing cost per processor even though total silicon area is larger.