die stacking
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**3D IC Integration and Die Stacking** encompasses the **technologies for vertically stacking multiple semiconductor dies and connecting them with through-silicon vias (TSVs), hybrid bonding, or other vertical interconnects** — creating three-dimensional integrated circuits that achieve higher bandwidth, lower power, greater heterogeneous integration density, and smaller footprint than equivalent 2D implementations.
**3D Stacking Approaches:**
```
Packaging Hierarchy (increasing integration density):
2.5D: Dies side-by-side on silicon interposer (CoWoS, EMIB)
Interconnect: RDL on interposer, 25-55μm bump pitch
BW: 100s GB/s between dies
Example: HBM stacks next to GPU on interposer
3D (TSV): Dies stacked vertically, connected by TSVs
Interconnect: TSVs (~5-10μm diameter, ~50μm pitch)
BW: TB/s (thousands of TSV connections)
Example: HBM DRAM stacks (4-16 die)
3D (Hybrid Bond): Die-to-die or wafer-to-wafer Cu-Cu direct bonding
Interconnect: sub-10μm pitch Cu pads
BW: Multi-TB/s (millions of connections)
Example: AMD V-Cache, Sony image sensors
Monolithic 3D: Sequential transistor fabrication on same wafer
Interconnect: Inter-layer vias at gate pitch
(research stage — CFET is a form of this)
```
**TSV Technology:**
| Parameter | Value |
|-----------|-------|
| TSV diameter | 5-10μm (fine), 20-50μm (coarse) |
| TSV pitch | 20-50μm (fine), 100-200μm (coarse) |
| TSV depth | 40-100μm (after die thinning) |
| Aspect ratio | 5:1 to 10:1 |
| Fill material | Electroplated copper |
| Liner/barrier | SiO₂ isolation + TaN/Ta + Cu seed |
| Resistance | <50mΩ per TSV |
| Capacitance | ~30-50fF per TSV |
| Process | Via-first, via-middle, or via-last |
**Hybrid Bonding:**
The most advanced D2D connection technology:
```
Process:
1. Prepare bonding surfaces: CMP Cu pads and SiO₂ dielectric
Surface roughness: <0.5nm RMS
Cu recess: 2-5nm below oxide surface
2. Surface activation: plasma treatment (N₂/O₂)
Creates hydrophilic surface for bonding
3. Room-temperature oxide bonding: face-to-face alignment
SiO₂-SiO₂ van der Waals bonding at room temperature
Alignment accuracy: <200nm (W2W), <500nm (D2W)
4. Anneal at 200-400°C: Cu expands, Cu-Cu metallic bond forms
Cu CTE (17ppm/°C) > SiO₂ CTE (0.5ppm/°C)
→ Cu pad pushes up and contacts opposing Cu pad
Result: Simultaneous electrical + mechanical bond at <10μm pitch
(10,000-1,000,000+ connections per mm²)
```
**Applications:**
| Application | Technology | Example |
|------------|-----------|--------|
| HBM memory | TSV stacking (8-16 die) | SK Hynix HBM3E |
| Cache stacking | Hybrid bonding (D2W) | AMD V-Cache (3D V-Cache) |
| Image sensors | Hybrid bonding (W2W) | Sony IMX stacked CIS |
| AI accelerators | 2.5D + 3D hybrid | NVIDIA B200, AMD MI300 |
| FPGA | Die stacking | Intel FPGA (Agilex) |
**Design Challenges:**
- **Thermal**: Bottom die in stack is farthest from heat sink. Power density limits: ~2W/mm² total for air-cooled stacked dies.
- **Testing**: KGD required before bonding (no rework possible after hybrid bonding).
- **Stress**: CTE mismatch between stacked dies causes warpage and stress on TSVs/bonds.
- **EDA**: 3D physical design tools must handle multi-die floorplanning, inter-die routing, and thermal co-optimization.
**3D IC integration is the primary scaling vector for the post-Moore era** — when lateral transistor scaling can no longer provide sufficient performance gains, vertical integration enables continued improvement in bandwidth density, functional density, and heterogeneous integration, making 3D stacking the defining technology trend in advanced semiconductor packaging.