die to die phy interface

**Die-to-Die PHY Interface Design** is **the physical layer circuit engineering for high-bandwidth, low-latency, energy-efficient interconnects between chiplets in multi-die packages — achieving data densities of 100+ Gbps/mm of die edge through parallel single-ended or differential signaling over short (<5 mm) in-package channels**. **D2D Signaling Approaches:** - **Ground-Referenced Signaling (GRS)**: single-ended voltage-mode signaling referenced to local ground — simpler than differential, 2× wire density per edge, but susceptible to ground bounce and crosstalk from SSO (simultaneous switching output) - **Differential Signaling**: pairs of complementary signals with embedded common-mode rejection — superior noise immunity but halves wire density per edge; used when signal integrity more challenging - **Forwarded Clock**: dedicated clock lane(s) distributed alongside data lanes — eliminates CDR complexity and latency, enables immediate data sampling at receiver; per-lane deskew handles routing length differences - **Source-Synchronous vs. Embedded Clock**: forwarded clock (source-synchronous) is standard for D2D due to short channels and the need for deterministic latency — embedded clock used only for longer reaches **UCIe (Universal Chiplet Interconnect Express):** - **Standard Specification**: open standard defining PHY and protocol layers for die-to-die interconnects — UCIe 1.0 supports standard (bumps) and advanced (hybrid bonding) packaging with bandwidth up to 1.3 TB/s per die edge - **Module Architecture**: 16 data lanes + 2 clock lanes per module in standard package; 64 data lanes + 8 clock lanes in advanced package — modules tiled along die edge to scale bandwidth - **Protocol Layer**: supports PCIe, CXL, and streaming protocols over the same PHY — protocol layer handles flow control, retry, and link training - **Bandwidth Density**: standard package achieves 28 Gbps/bump at 100 μm pitch; advanced package achieves 3.5 Gbps/bump at 25 μm pitch — advanced packaging enables >1 Tbps/mm edge bandwidth **PHY Circuit Design:** - **TX Driver**: small low-swing voltage-mode driver (200-400 mV swing) — minimal output impedance matching needed for sub-5mm channels; power efficiency <0.5 pJ/bit at 16 Gbps per lane - **RX Receiver**: simple sense amplifier or continuous-time comparator — short channel eliminates need for equalization (no CTLE/DFE required), reducing complexity and latency - **Per-Lane Deskew**: programmable delay elements on each lane compensate for routing length differences between lanes — deskew range of ±1 UI with sub-10 ps resolution - **Built-In Self-Test**: integrated PRBS generator and checker for link validation — eye diagram measurement and BER testing during manufacturing and initialization **Die-to-die PHY design is the key enabling technology for the chiplet revolution — achieving the bandwidth density and energy efficiency needed to make multi-die architectures competitive with monolithic designs while enabling heterogeneous integration of dies from different process nodes and foundries.**