dielectric breakdown
**Dielectric Breakdown and TDDB** is the **reliability degradation mechanism where the gate dielectric progressively accumulates defects under electrical stress until a conductive path forms through the oxide** — leading to transistor failure, with Time-Dependent Dielectric Breakdown (TDDB) being the key metric that determines whether the gate oxide will survive the product's specified operating lifetime (typically 10 years at operating conditions).
**Breakdown Mechanism**
1. **Trap generation**: Electrical stress (high field, ~5-10 MV/cm) creates defect sites (traps) in the dielectric.
2. **Trap accumulation**: Traps randomly generated throughout oxide volume over time.
3. **Percolation path**: When enough traps connect from gate to channel → conductive path forms.
4. **Hard breakdown**: Sudden increase in gate leakage by 100-1000x → transistor failure.
5. **Soft breakdown**: Partial percolation path → noisy, elevated leakage → gradual degradation.
**TDDB Testing**
- **Accelerated testing**: Apply higher-than-operating voltage (stress voltage) at elevated temperature.
- **Measure**: Time to breakdown for each test structure.
- **Statistical analysis**: Weibull distribution → extract shape parameter (β) and characteristic lifetime (t63%).
- **Extrapolation**: Use voltage acceleration model to project lifetime at operating conditions.
**Voltage Acceleration Models**
| Model | Equation | Application |
|-------|----------|------------|
| E-model | $TTF \propto e^{-\gamma E}$ | Thicker oxides (> 5 nm) |
| 1/E-model | $TTF \propto e^{G/E}$ | Thin oxides, high field |
| Power-law | $TTF \propto V^{-n}$ | High-k dielectrics |
- Temperature acceleration: $TTF \propto e^{E_a/kT}$ with Ea ~ 0.5-0.7 eV.
- Combined voltage + temperature acceleration: Enables 10-year projection from hours of testing.
**TDDB at Advanced Nodes**
- **Gate oxide**: SiO2 interfacial layer (~0.5 nm) + HfO2 high-k (~1.5 nm).
- **Electric field**: Despite lower voltage (0.7-0.8V), thinner oxide means field > 5 MV/cm.
- **High-k advantage**: HfO2 has fewer intrinsic defects than ultra-thin SiO2 → better TDDB.
- **Reliability margin**: Must demonstrate < 0.01% failure rate at 10 years, 125°C, operating voltage.
**BEOL Dielectric Reliability**
- TDDB also applies to inter-metal dielectrics (low-k SiCOH).
- Adjacent metal lines at different voltages stress the low-k dielectric between them.
- Low-k is porous → more susceptible to moisture and copper drift → reduced TDDB lifetime.
- Low-k TDDB is becoming a limiter at advanced nodes where line spacing < 20 nm.
**Product Qualification**
- Foundry qualification requires TDDB testing at multiple voltages and temperatures.
- Data reported as **Weibull plot**: Cumulative failure vs. time-to-failure.
- Customer requirement: $TTF_{0.01\%}$ > 10 years at use conditions (Vdd, 105°C junction).
TDDB is **one of the most critical reliability qualifications for any semiconductor product** — if the gate dielectric cannot survive the rated voltage for the product lifetime, the chip will fail in the field, making TDDB margin a fundamental constraint on supply voltage scaling and oxide thickness reduction at every node.