Diffused Base 1954 Verify Finished Slice Dimensions
# Verify Finished Slice Dimensions: Measuring What Margin Actually Survived, Not What Step 6 Budgeted
This step measures the wafer's actual thickness, flatness, and usable area after lapping, etching, and rinsing are all complete — and it exists because Step 6's collector-margin budget was a calculation made in advance, while this step is the first point in the sequence that measures what margin the wafer actually carries into the furnace. Three separate operations have each had a chance to spend part of that budget since it was set: Step 7's lapping could have left a wedge, Step 8's etch could have run long, and even Step 9's rinse, if mishandled, could have left the surface in a state this process would rather not diffuse into. This step is the single checkpoint that catches the combined effect of all three before any dopant schedule begins.
## 1. The Measured Margin, Not the Budgeted One, Is What the Diffusion Schedule Actually Gets
Measured finished thickness $t_{\text{measured}}$ differs from the thickness Step 6 originally budgeted, $t_{\text{budgeted}}$, by the sum of every small deviation $\delta_i$ introduced since — a wedge left by lapping, an over-etch, any thickness lost to multiple rinse cycles. No single one of those earlier steps necessarily violated its own specification; each could pass its own local check while still contributing a few micrometers to a combined deviation large enough to matter once Step 14's drive-in actually tries to place a junction a fixed depth beneath this now-uncertain surface. This step exists specifically because no earlier step in the sequence was positioned to see that combined total.
## 2. Real Diagram: Three Small, Individually Acceptable Deviations Add Up to One That Is Not
## 3. Usable Area Still Has to Be Mapped, Not Just Averaged
Usable area $A_{\text{usable}}$ excludes any region where resistivity or thickness drifts outside this process's acceptance window — a mapping exercise, not a single-point measurement, because this process's later diffusions treat every point on the wafer identically, with no mechanism to locally compensate for a region that happened to drift during an earlier step. A wafer that averages acceptably across its full area but carries a hidden exclusion zone near one edge still produces devices in that zone with a different base width than devices cut from the center, a difference this step's area-wide measurement is the only chance in the sequence to catch before committing the whole wafer to a furnace run.
## Verify Finished Slice Dimensions's Place in the Process Lineage
Verifying finished slice dimensions is step ten of Bell Labs' twenty-six-step diffused-base manufacturing sequence — immediately after rinsing and drying, and before the wafer is ever loaded into a diffusion furnace. It is the one checkpoint positioned to catch the combined deviation left by three separate earlier steps, each of which could pass its own local specification while still contributing to a total this process cannot afford once a fixed-depth junction is driven beneath whatever margin actually survives. Step eleven, loading the wafer and establishing the furnace atmosphere, proceeds only with sections this step has actually confirmed.