Diode Connected MOSFET
# Diode-Connected MOSFET: Turn a Bias Current into a Voltage
A diode-connected MOSFET has its gate tied to its drain. The resulting two-terminal connection converts an imposed current into the VGS required for that transistor to conduct it. This is a basic building block for bias generation, current mirrors and active loads.
The term describes the connection. The useful forward characteristic comes from the gate-controlled channel; it is distinct from the transistor’s intrinsic body diode, which is a pn junction with its own polarity and operating limits.
## 1. Follow the shorted gate and drain
*Conceptual enhancement-mode NMOS. Source and body are held at the lower reference; the body connection is omitted from the symbol. The external reference-current source needs enough compliance voltage to establish the operating point.*
With gate and drain connected, VDS = VGS. If the reference node rises, VGS increases and the channel draws more current. The node settles where transistor current balances the injected current. Gate leakage is neglected in this description.
For a positive-threshold, long-channel NMOS in strong inversion, the saturation condition VDS ≥ VGS − VT is satisfied by VDS = VGS. This statement assumes the intended forward bias and a device operating within its voltage limits. It does not mean the device is always on, and the simple strong-inversion criterion is not a universal model for every MOS technology.
## 2. Separate DC drop from small-signal resistance
*Analytical example using ID = β(V − VT)²/2 above threshold, with β = 1 mA/V² and VT = 0.4 V. Subthreshold current, body effect and channel-length modulation are excluded. These curves are not measured or PDK-simulated data.*
At V = 0.8 V, overdrive is 0.4 V and the model gives ID = 80 µA. Its DC ratio is V/ID = 10 kilohms. But a small perturbation sees the local derivative: gm = β(V − VT) = 0.4 mS, so the incremental resistance is 1/gm = 2.5 kilohms. The gray secant and green tangent in the chart explain why these two resistance values differ.
More generally, with source and body fixed, a perturbation at the shorted gate/drain changes both VGS and VDS. The node conductance is gm + gds, giving r ≈ 1/(gm + gds) at low frequency. Body transconductance does not add a separate term in this test because source-to-body voltage is unchanged. If the source or body moves, rederive the port model for those connections.
## 3. Use the voltage as a reference, with limits
In a simple current mirror, the diode-connected reference transistor creates a gate bias for another transistor. Similar devices at the same VGS and temperature can produce related drain currents, with geometry setting the nominal ratio. Output voltage, mismatch and device behavior determine the actual accuracy; the reference connection alone does not guarantee an exact current copy.
A reference node also has finite resistance and capacitance. Attaching additional gates or wiring increases its capacitive load. Injected signal current, leakage or a changing reference current can move the bias voltage, so the node is not an ideal voltage source.
| Quantity | Useful interpretation | Main check |
|---|---|---|
| DC node voltage | VGS needed for the imposed current | Model, geometry, current and temperature |
| Incremental resistance | Inverse local current slope | gm, gds and terminal connections |
| Bias-node settling | Response of the loaded reference node | Capacitance, drive current and operating point |
| Mirror output current | Current generated by a separate biased device | Matching, output compliance and drain voltage |
## 4. Verify it in the intended circuit
Sweep the imposed current and inspect VGS, current density and device voltage limits. Extract small-signal resistance with source and body connected as in the real design; compare it with gm and gds at the actual diode-connected operating point.
Use the PDK model for weak inversion and short-channel behavior rather than extending the illustrative square law beyond its assumptions. Check process and temperature variation, startup, leakage and the settling of all attached gate capacitances. If the reference current comes from a self-biased loop, startup must be checked for the complete loop.
For PMOS, the analogous gate-to-drain connection uses the corresponding voltage and current polarities. In either case, distinguish the intended channel conduction from body-junction conduction and keep all junction and oxide voltages within the device limits.
## References
- [JKU: First Circuit — MOSFET Diode](https://iic-jku.github.io/analog-circuit-design/slides/diode.html) — connection, bias feedback and operating-point analysis.
- [Analog Devices: The Current Mirror](https://wiki.analog.com/university/courses/electronics/text/chapter-11) — current-to-voltage reference and mirror operation.