Lateral Sige Recess

The lateral SiGe recess demands exactly the opposite chemistry goal from the superlattice stack etch that immediately precedes it — where that round needed near-equal Si and SiGe etch rates to avoid an unwanted scalloped sidewall, this round needs extreme selectivity between the same two materials, etching SiGe away rapidly while leaving the silicon layers essentially untouched. This etch also runs in a direction almost nothing else in this entire project has used: isotropic, sideways removal through the opening the previous vertical etch already created, undercutting into each SiGe layer from the exposed sidewall rather than cutting straight down from a top surface the way nearly every anisotropic etch covered before it has worked.

Two consecutive rounds asking for opposite selectivity on the identical pair of materials is a genuinely unusual sequence, and stating that reversal explicitly is the clearest way to see why each round's chemistry choice makes sense on its own terms. The superlattice stack etch needed Si and SiGe to disappear at nearly the same rate so a single continuous cut could pass through the whole alternating stack without rippling; this recess instead needs SiGe to disappear while silicon survives almost completely intact, because the entire point of this step is removing the sacrificial material while preserving the layers that will actually function as the device — the two etches aren't contradictory, they're solving two different problems using the same material pair at two different points in the same process flow, each tuned toward whatever selectivity that specific problem needs.

Lateral recess distance, not etch depth, is the actual device parameter this step sets, which is another instance of this project's recurring theme that a controlled, partial removal can be the real engineering target rather than a side effect to tolerate. How far the etch undercuts sideways into each SiGe layer directly determines the width of the gap left behind once that layer is gone, and that gap width is exactly the space a later gate deposition step will fill to wrap around the released silicon layer — too little lateral recess leaves insufficient room for a properly formed gate; too much risks undermining the mechanical support holding the released silicon layers in place before the gate material can be deposited to replace that support, which makes recess distance uniformity across every opening on the wafer the actual metric this etch gets qualified against, not simply whether the SiGe cleared.

Read through a distance-not-depth lens, the lateral SiGe recess closes the loop this project opened with the superlattice stack etch — the sacrificial SiGe that round carved a clean opening through is now the material this round removes entirely, in a direction almost nothing else here has used, measured by a lateral gap width rather than a vertical clearance, because the real goal was never removing SiGe for its own sake but creating exactly the right amount of empty space for a gate structure that hasn't been built yet.