DRAM Sti
# DRAM STI: Shallow Trench Isolation Architecture, Corner-Leakage Theory, and the Cell-to-Cell Isolation Moat
Shallow trench isolation (STI) is the etched, oxide-filled moat that separates one transistor's silicon from its neighbor's. In logic, STI is a commodity step every foundry runs the same way. In DRAM it is not: a 1T1C array packs access transistors closer together than almost any other structure in a chip, uses a word line that is itself buried inside the silicon right next to the trench, and fails in a way logic never does — if the trench lets two adjacent cells talk to each other electrically, one cell's "1" leaks into its neighbor's "0," corrupting data that was never even accessed. STI is the reason that doesn't happen, and getting it to not happen at DRAM's pitch is a much harder problem than the name "shallow" suggests.
The isolation failure mode is not a leaky transistor — it is a parasitic one. A sharp, un-rounded corner where the active area meets the trench sidewall concentrates the electric field from the nearby word line far more than the flat channel does, which locally lowers the effective threshold voltage right at that corner. The result behaves exactly like a second, parallel transistor hiding at the edge of the real one, turning on earlier than the main device and conducting a leakage current that the main device's gate never intended:
This shows up on a transistor's subthreshold curve as a "hump" — a kink where the current stops falling as fast as gate voltage drops, because the corner's parasitic path is still conducting after the main channel has shut off. Rounding the trench corner during a post-etch anneal, and tuning the liner and channel-stop implant beneath the trench, are the standard fixes — all aimed at pushing $\Delta V_{th,\text{corner}}$ toward zero.
| Era / node class | Isolation method | Fill chemistry | Typical aspect ratio | Dominant failure mode |
|---|---|---|---|---|
| Pre-1990s | LOCOS (local oxidation) | Thermal oxide, lateral bird's-beak | ~1:1 | Area waste, encroachment |
| 1990s logic | Early STI | PECVD oxide | ~2–3:1 | Corner leakage, dishing |
| 2000s logic | Mature STI | HDP-CVD oxide | ~4–6:1 | Stress-induced mobility shift |
| DRAM, 2010s | Scaled STI + buried word line | O3-TEOS SACVD | ~6–8:1 | Seam voids, cell-to-cell leakage |
| DRAM, current (1β/1γ-class) | Scaled STI + saddle-fin BWL | Flowable CVD / spin-on dielectric | ~8–10:1 | Void-free fill at extreme AR |
Gap-fill feasibility, not etch, is what actually caps how narrow the trench can get. A trench's aspect ratio is simply $AR = D_{trench}/W_{trench}$, and any deposition that grows film on the sidewalls as fast as it grows on the trench floor will pinch the opening closed — forming a buried seam or keyhole void — once the sidewall film thickness reaches roughly half the trench width, long before the bottom has filled. That geometric trap is why DRAM abandoned directional HDP-CVD oxide for the narrowest, deepest STI trenches in favor of flowable CVD and spin-on dielectric chemistries, which fill from the bottom up like a liquid rather than conformally coating every wall at once. A single missed void doesn't just fail one cell — it can create an electrical short between two adjacent bit lines, which is a harder failure to screen out than a single weak capacitor.
STI also quietly sets part of the sensing budget covered in the 1T1C cell's read equation. The trench between two adjacent active areas is itself a parasitic capacitor, and its edge-to-edge coupling adds directly into the bit-line parasitic capacitance term $C_{BL}$ that appears in $\Delta V = V_{cell} \cdot C_s/(C_s + C_{BL})$: a narrower, less effective trench doesn't just risk leakage, it also raises $C_{BL}$ and shrinks the sense margin on every read. Isolation and sensing are not two separate problems in DRAM — they are the same trench viewed from two different equations.
Zoom out from one trench to the array, and the same pattern just repeats. A DRAM array is a checkerboard of active-area stripes and STI stripes, crossed at a right angle by buried word lines that behave identically whether they happen to be sitting over silicon or over oxide — the word line doesn't know the difference, which is exactly the point.
That makes trench scaling its own capital moat, structurally identical to the storage capacitor's. Every node shrinks the trench width while the depth barely changes, so the aspect ratio that must be filled void-free climbs every generation — exactly the same one-way ratchet that forced the storage capacitor from 10:1 to 80:1 over the same decades. Only Samsung, SK hynix, and Micron currently run void-free gap-fill at DRAM's tightest pitches at competitive yield, and the process knowledge for doing it — the exact flowable-CVD precursor chemistry, cure schedule, and corner-rounding anneal that avoids both voids and the subthreshold hump at the same time — is proprietary, decades-deep, and not something a trailing fab can shortcut by buying the same deposition tool off the shelf.
Read DRAM STI through an *aspect-ratio-and-corner-field* lens rather than a *"just an oxide trench"* lens: the width keeps shrinking, the depth barely does, so $AR = D_{trench}/W_{trench}$ climbs every node exactly like the storage capacitor's does, and every engineering response — a rounded corner to kill $\Delta V_{th,\text{corner}}$, a channel-stop implant to block punchthrough, a flowable fill to avoid a seam void — is a different tactic for keeping one trench from ever letting two neighboring cells' charge, or leakage, cross between them.