4f2 Vertical Channel Transistor

Every etch covered across this entire project so far, from the storage-node hole through the TSV and even the bevel etch, has removed material to create a cavity or a cleared surface; the vertical channel pillar etch inverts that logic completely, because the actual functional transistor channel is the silicon left standing after the etch, not the space the etch clears away. This etch belongs to a fundamentally different, not-yet-mainstream DRAM cell architecture — the 4F² vertical channel transistor, sometimes called VCT — which orients the access transistor's channel vertically as a tall, narrow pillar instead of the horizontal buried-gate geometry every production DRAM cell covered earlier in this project actually uses; everything in Sections 1 through 10 described established, in-production process steps, while this etch and the rest of Section 11 describe emerging technology still working toward production viability.

Decoupling channel length from horizontal footprint is the whole reason this architecture exists, and it's a genuinely different density lever from anything a horizontal buried-gate cell can offer. A horizontal channel's length is directly tied to how much X-Y area the cell consumes, so shrinking a horizontal cell's footprint inevitably shortens its channel and worsens leakage and short-channel effects; a vertical pillar's channel length is instead set by the pillar's height, which can grow taller without consuming any additional horizontal die area at all — this is precisely the density unlock 4F² architectures chase, trading a manufacturing problem (etching a tall, uniform pillar) for a scaling problem (shrinking a horizontal footprint) that horizontal cells eventually run out of room to solve.

Diameter uniformity along the pillar's entire height matters here for a completely different reason than the bowing control this project's storage-node hole etch cared about. The storage-node hole etch needed its hole to actually reach full depth without narrowing so badly partway down that the bottom never cleared; this pillar etch instead needs the standing silicon column's width to stay consistent along its whole height because that width is now the transistor's channel width at every point along the current path, and any taper or bulge introduces a local threshold-voltage and leakage variation along the channel's own length — a defect mode with no real equivalent in any negative-space etch covered earlier in this project, because those etches never had their own removed material's remaining shape function as an active device region.

Read through a positive-structure lens, the vertical channel pillar etch opens Section 11 by introducing the one category of etch this entire project's negative-space framing never had to address — a process step whose success is defined by the shape and uniformity of the material that survives the etch, not the cleanliness or depth of the cavity it creates, which is a fitting place for this sequence to turn from documenting established production technology toward the architecture that might eventually replace parts of it.