edge exclusion

Edge exclusion is the outer region of a wafer where processes may be less controlled and chips are not expected to yield, defining the usable die area boundary. Definition: typically 2-3mm from wafer edge where lithography, etch, CMP, and deposition performance degrades. Causes of edge effects: (1) Lithography—edge die partial exposure, defocus from wafer bow at edge; (2) Etch—different plasma characteristics at wafer edge (loading, temperature); (3) CMP—pad pressure variation, edge over-polish or under-polish; (4) CVD/PVD—gas flow and temperature non-uniformity near edge; (5) Resist coating—edge bead region, resist thickness variation. Edge exclusion reduction: shrinking from 3mm to 2mm or less to capture additional die—significant yield impact on large die. Edge die: partially exposed die at wafer periphery—some fabs attempt to salvage edge die with special processing. Metrology: dedicated edge measurements, separate SPC for edge sites. Edge-specific processes: edge bead removal (EBR), edge exposure (WEE), edge trim CMP. Edge ring effects: in etch/CVD, focus ring and edge ring design affects plasma uniformity at wafer edge. Impact: reducing edge exclusion by 1mm on 300mm wafer can add 1-3% more die (dozens of chips depending on die size). Advanced challenges: EUV edge placement, edge die yield improvement programs. Ongoing focus area for maximizing wafer-level yield and die output per wafer.