electromigration
**Electromigration (EM)** is the transport of metal atoms along an interconnect driven by the momentum transfer from current-carrying electrons — the electron wind pushes atoms in the direction of electron flow, gradually creating voids where atoms leave and hillocks where they accumulate. A void that spans the full cross-section of a wire causes an open-circuit failure; a hillock that bridges to an adjacent line causes a short. EM is the dominant wearout mechanism for on-chip copper interconnects and the primary constraint on how much current a metal line can carry in a 10-year product lifetime. The CFS Interconnect Simulator at /interconnect models Black's-equation lifetime directly.
**Black's equation — the lifetime model.** The empirical law that governs EM sign-off in every foundry PDK:
$$\text{MTTF} = A \cdot J^{-n} \cdot \exp\!\Bigl(\frac{E_a}{k_B T}\Bigr)$$
where MTTF is median time to failure, $J$ is current density (MA/cm²), $n$ is the current-density exponent (typically 1–2; $n=2$ for void-growth-limited, $n=1$ for void-nucleation-limited), $E_a$ is the activation energy for the dominant diffusion path, $k_B$ is Boltzmann's constant, $T$ is absolute temperature (K), and $A$ is a process-dependent prefactor. The equation shows the extreme sensitivity to both current density (quadratic) and temperature (exponential via Arrhenius).
**Diffusion paths — which atoms move and where.** In copper dual-damascene interconnects, atomic diffusion can occur along four paths, each with a different activation energy:
| Diffusion path | $E_a$ (eV) | Dominates when | Notes |
|---|---|---|---|
| Cu/cap interface (top surface) | 0.7–0.9 | Most common in advanced nodes | Between Cu and SiCN/SiN cap; primary EM path in modern BEOL |
| Grain boundary | 0.9–1.1 | Small grains, bamboo failure | Becomes less important with large-grain Cu (annealing) |
| Bulk (lattice) | 2.0–2.2 | Very high T (rare in operation) | Negligible at normal chip temperatures |
| Cu/barrier interface (sidewall) | 0.8–1.0 | Thin or damaged barriers | TaN/Ta liner; secondary path |
The lowest-$E_a$ path dominates lifetime. In modern Cu BEOL (45 nm and below), the Cu/cap interface is usually the weakest link — which is why cap material engineering (CoWP selective cap, SiCN optimization, graphene barrier) is the primary EM improvement lever.
**The Blech effect — short wires don't fail.** Below a critical length–current-density product $(J \cdot L)_{\text{crit}}$, a back-stress (compressive at the anode end, tensile at the cathode end) builds up that exactly balances the electron-wind force. The wire reaches a steady state with no net atomic flux — it is "immortal" with respect to EM. The Blech threshold for copper is approximately:
$$(J \cdot L)_{\text{crit}} \approx \frac{\Omega \cdot \sigma_{\text{crit}}}{q^* \cdot \rho} \approx 3000\text{–}5000 \; \text{A/cm}$$
where $\Omega$ is the atomic volume of Cu, $\sigma_{\text{crit}}$ is the critical back-stress (~100–500 MPa depending on confinement), $q^*$ is the effective charge, and $\rho$ is resistivity. For a typical M1 line at 28 nm node ($L \approx$ 10–50 µm), the Blech limit allows significantly higher current densities than Black's equation alone would predict — EDA tools exploit this during EM sign-off to avoid false violations on short segments.
**Void nucleation and growth.** The physical failure sequence:
1. **Stress accumulation.** Current flow builds tensile stress at the cathode end of a line segment (atoms are swept toward the anode). Stress is highest at flux-divergence sites: diffusion-barrier boundaries, via bottoms, width transitions.
2. **Void nucleation.** When tensile stress exceeds the critical nucleation stress (~100–200 MPa), a void nucleates — typically at the Cu/cap interface directly below the via.
3. **Void growth.** Continued current drives more atoms away from the void site; the void grows along the Cu/cap interface until it spans the full wire width.
4. **Resistance increase and failure.** A fully spanning void forces current through the thin barrier liner (TaN, ~200 Ω/□) or disconnects the via entirely → open-circuit failure.
**EM design rules — what the PDK specifies.** Every foundry defines maximum current-density limits per metal layer and via type, typically at 105°C junction temperature and 10-year lifetime:
| Metal layer | Width (nm) | $J_{\text{max,DC}}$ (MA/cm²) | $J_{\text{max,AC}}$ (MA/cm²) | Temperature derating |
|---|---|---|---|---|
| M1 (finest) | 20–28 | 1.0–1.5 | 3–5 | −50%/+10°C above 105°C |
| M2–M4 | 28–40 | 1.5–2.5 | 5–8 | Same Arrhenius scaling |
| Upper metals | 80–400 | 3–6 | 10–20 | Power grid, relaxed rules |
| Top metal (AP) | 800–3000 | 5–10 | 15–30 | Thick redistribution layer |
| Via (single) | 20–40 | per-via current limit: 0.1–0.5 mA | — | Redundant vias strongly recommended |
AC (bidirectional) current allows ~3× higher density than DC because atoms swept in one direction are swept back in the next half-cycle (healing effect, duty-factor dependent).
**Self-heating amplifies EM.** At advanced nodes, narrow wires (20–28 nm width) have high resistivity (Fuchs–Sondheimer size effects push Cu $\rho$ to 4–8 µΩ·cm vs bulk 1.7). Joule heating raises local wire temperature 10–30°C above the substrate — and because Black's equation is exponential in T, even 10°C of self-heating can halve the EM lifetime. EM sign-off tools at 5 nm and below must couple thermal simulation with current-density extraction.
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**EM mitigation at advanced nodes.** The industry fights EM on multiple fronts: (1) **cap engineering** — replacing SiCN with cobalt or ruthenium selective caps that bond more strongly to Cu, raising $E_a$ by 0.1–0.2 eV (doubles lifetime); (2) **redundant vias** — placing 2–4 vias at every connection so a single-via void doesn't kill the net; (3) **wide-wire slotting** — inserting slots in power lines to reduce effective electron-wind force while maintaining cross-section; (4) **Cu alloy doping** — adding 1–2% Mn or Al to Cu, which segregates to grain boundaries and the cap interface, pinning diffusion; (5) **alternative metals** — cobalt and ruthenium lines at M0/M1 have higher EM resistance than Cu at sub-20 nm widths due to shorter mean free path (no size-effect blow-up).
**EM sign-off flow in EDA.** After routing, an EM checker (Cadence Voltus, Synopsys RedHawk) extracts per-segment current density from power-grid and signal-net simulations, applies Black's equation with temperature from thermal analysis, flags violations, and proposes fixes (wider wires, shorter segments, more vias, lower resistance paths). At 3 nm, EM sign-off iterations consume 15–25% of total physical-design closure time — second only to timing closure.