end-of-range defects
**End-of-Range (EOR) Defects** are **dislocation loops formed at the amorphous-crystalline interface left by heavy ion implantation** — they mark the depth where ions came to rest and lattice damage was maximized, representing the most concentrated defect band in implanted silicon and a persistent source of junction leakage and interstitials.
**What Are End-of-Range Defects?**
- **Definition**: A planar band of dislocation loops and interstitial clusters located at the depth corresponding to the projected range of a heavy implant species (typically germanium, indium, or silicon pre-amorphization implants) — the boundary between the amorphized surface layer and the underlying crystalline substrate.
- **Formation Mechanism**: Heavy ion implantation amorphizes the surface layer above Rp (projected range). During subsequent solid-phase epitaxial regrowth anneal, excess silicon interstitials generated at the amorphous-crystalline boundary condense into stable {311} defects and Frank dislocation loops that resist dissolution.
- **Depth Location**: EOR defects lie precisely at the amorphous-crystalline interface depth, which can be engineered by adjusting the implant energy and species. For a 30keV germanium PAI in silicon, EOR defects typically form at 30-50nm depth.
- **Interstitial Source**: Even after the amorphous layer fully regrows, EOR loops remain as stable interstitial reservoirs that slowly dissolve during subsequent annealing, releasing interstitials that drive transient enhanced diffusion of nearby boron.
**Why EOR Defects Matter**
- **Junction Leakage**: If EOR dislocation loops are located within the depletion region of a p-n junction — or if they survive into the final device — they act as generation-recombination centers that produce excess leakage current orders of magnitude above the bulk generation rate.
- **SRAM and DRAM Retention**: Leakage from EOR defects in or near storage node junctions degrades charge retention time in DRAM and raises the minimum supply voltage for SRAM data retention in near-threshold operation.
- **TED Driving Source**: EOR loops are the primary long-term interstitial reservoir feeding transient enhanced diffusion — controlling their depth, density, and dissolution rate is critical to controlling boron profile spreading.
- **Gettering Function**: EOR defects preferentially trap metallic impurities (copper, iron, nickel) before they can reach the active transistor region, a beneficial gettering effect exploited in some device architectures.
- **Characterization Marker**: The depth and morphology of EOR defects observed in transmission electron microscopy provide a standard calibration metric for implant damage models in TCAD process simulation.
**How EOR Defects Are Managed**
- **PAI Depth Engineering**: Pre-amorphization implant energy is selected to place EOR defects well below the intended junction depth, ensuring they lie outside the depletion region where leakage generation would be most harmful.
- **Co-Implant with Carbon**: Carbon implanted at the PAI depth traps interstitials and suppresses loop growth, reducing EOR loop density and limiting their duration as a TED source.
- **Anneal Optimization**: Higher temperature anneals dissolve EOR loops faster, but must be balanced against diffusion of active dopants — millisecond laser annealing activates dopants before EOR defects have time to generate significant interstitial emission.
End-of-Range Defects are **the inescapable scar of amorphizing ion implantation** — managing their depth, density, and dissolution behavior is essential for controlling both transient enhanced diffusion and junction leakage in every advanced CMOS source/drain process.