etch damage

**Plasma etching (dry etching)** is how almost every fine feature on a modern chip is carved. A low-pressure gas is energized into a plasma of positive ions and chemically reactive radicals; the radicals react with the exposed film to form volatile byproducts that are pumped away, while a vertical electric field in the plasma **sheath** accelerates ions straight down onto the wafer. That combination is what makes etching **anisotropic** — it cuts straight down through the mask opening without eating sideways under the mask, so features stay vertical.\n\nTwo properties define an etch process. **Selectivity** is how much faster the target film etches than the mask or the layer underneath, and **aspect ratio** is trench depth divided by width. As devices go 3D, aspect ratios have exploded, and holding a vertical profile tens of microns deep without bowing, tapering, or twisting is the hardest problem in the fab.\n\n```svg\n\n```\n\n**Why etch is the AI-era chokepoint.** The memory and logic that feed AI accelerators are built on the most punishing etches in the industry. A 3D NAND stack is now hundreds of layers tall, and its channel holes are etched as single high-aspect-ratio features more than 10 µm deep. Gate-all-around (GAA) logic makes it worse: Samsung's 3 nm nanosheet flow needs roughly 11 discrete plasma-etch steps to release the suspended nanosheets, versus about 6 for the FinFET it replaces. Etch step-count, not just lithography, now scales with every node.\n\n**Cryogenic and atomic-layer precision.** To hold profile at these depths, the tooling has moved to two frontiers. Cryogenic etch runs the wafer far below room temperature to sharpen sidewalls and speed removal — Lam's Cryo 3.0 reports under 0.1 percent critical-dimension deviation at 10 µm depth in 3D NAND channel holes, with more than double the etch rate of conventional dielectric processes. In parallel, **atomic layer etching (ALE)** removes material one self-limiting monolayer per cycle — a surface-modification step followed by a removal step — giving angstrom-level control for GAA and DRAM. The ALE tool market alone is projected to roughly double from about 1.36 billion dollars in 2025 to 2.74 billion by 2033.\n\n**Read through a quant lens rather than a chemistry lens,** and etch is a concentrated, cycle-amplified bet on advanced-node and 3D scaling. The plasma-etch system market was about 10.18 billion dollars in 2026 and is modeled to reach 23.21 billion by 2035 at a 12.5 percent CAGR, and three suppliers — Lam Research, Tokyo Electron, and Applied Materials — ship roughly 80 to 85 percent of new etch platforms, with Lam tools present in about 80 percent of sub-5 nm manufacturing. Because etch step-count rises with every 3D and GAA node, etch-tool bookings tend to lead accelerator-capacity ramps, which is why the sell side watches them alongside CoWoS allocation. RIE versus ICP source design, fluorocarbon dielectric chemistries, ARDE and aspect-ratio-dependent etching, and endpoint detection by optical emission are all natural next layers to go deeper on.