feol process

**FEOL (Front End of Line)** — the portion of chip fabrication that creates the transistors themselves, from bare silicon wafer through completed gate and source/drain structures. **FEOL Process Sequence** 1. **Well formation**: Ion implant p-well and n-well regions 2. **STI (Shallow Trench Isolation)**: Etch + fill trenches to isolate transistors 3. **Gate stack formation**: Grow gate dielectric (SiO₂ + HfO₂), deposit gate electrode (poly-Si or metal) 4. **Gate patterning**: Lithography + etch to define gate length (critical dimension) 5. **Halo + LDD implants**: Control short-channel effects 6. **Spacer formation**: Define S/D offset from gate 7. **Source/drain implant**: Heavy doping for low-resistance S/D 8. **Activation anneal**: Activate dopants and repair implant damage 9. **Silicide formation**: Reduce contact resistance on S/D and gate 10. **Contact etch stop layer (CESL)**: Deposit stressed SiN for strain engineering **Key Metrics** - Gate length: 5–30nm depending on node - Gate oxide (EOT): 0.5–1.0nm - Junction depth: 5–15nm - All dimensions controlled to sub-nanometer precision **FEOL at Different Nodes** - Planar MOSFET: Through ~22nm - FinFET: 22nm–3nm - GAA/Nanosheet: 3nm and beyond **FEOL** defines the intrinsic transistor performance — everything in BEOL is just connecting what FEOL built.