Fin Bending Fin Collapse

# Fin Bending and Fin Collapse

A FinFET's whole electrostatic advantage comes from its fin being tall and thin — gate control wrapping three sides of a narrow silicon sliver instead of one flat surface. That same geometry is a mechanical liability every fin has to survive through dozens of process steps before the transistor is finished: a structure with that little cross-sectional area relative to its height is inherently prone to bending, and under the wrong combination of force and support, outright toppling over and collapsing into its neighbor.

The same capillary mechanism that topples resist lines during wet processing attacks silicon fins for exactly the same structural reason — tall, narrow, and weakly anchored at the base. Every wet clean and rinse step the fin survives between patterning and the gate stack going down leaves liquid sitting in the narrow trenches between adjacent fins, and as that liquid dries, the retreating meniscus pulls neighboring fins toward each other with real lateral force — the identical physics covered for resist pattern collapse (id 562), just acting on silicon instead of polymer. Silicon fins are stiffer than resist, which buys some margin, but at the aspect ratios modern FinFET processes actually use — fin height several times its width — that stiffness advantage isn't enough to make the risk disappear, just enough to push the failure threshold to a narrower, taller fin than resist alone would tolerate.

Fin collapse is a catastrophic yield event, not a performance-degrading one, because two bent fins touching each other create a dead short between structures that must stay electrically isolated. A partially bent but still-separated fin can sometimes survive as a slightly degraded device; a fully collapsed fin pair bridging across the gap between them creates a direct short that fails the device outright, and because collapse tends to happen in clusters — the same wet-process conditions affect every fin in a region simultaneously — a single bad clean or dry step can take out a whole patch of the array at once rather than one isolated transistor. That clustering behavior makes fin collapse show up as a distinctive spatial signature on a wafer map, which is often how fabs first identify that a specific process step has drifted into collapse-risk territory.

Spacer and liner support structures left intentionally in place during the most vulnerable wet steps reduce collapse risk by giving fins lateral mechanical backing they wouldn't otherwise have. Rather than leaving fins fully exposed and self-supporting through every wet process step, some integration schemes deliberately delay removing a protective liner or spacer film until after the highest-risk cleans are complete, trading an extra process step and some added complexity for mechanical support exactly when the fins are most exposed. Dry or supercritical drying techniques — the same no-capillary-meniscus approaches covered for resist pattern collapse — apply equally well here, since the physics driving the failure is identical regardless of which material is at risk.

Resist pattern collapse (562) happens to a sacrificial polymer pattern that gets stripped away later regardless. Fin collapse happens to the permanent silicon structure the entire transistor is built around — which is exactly why it's treated as a hard yield-limiting failure mode rather than a correctable process variation, with no equivalent to simply re-coating and re-patterning a failed resist layer.