final test yield
**Final test yield** is the **percentage of packaged integrated circuits that pass all electrical tests after assembly** — representing the last quality gate before products ship to customers, capturing the cumulative effect of fab, assembly, and test processes, and directly determining product availability and manufacturing profitability.
**What Is Final Test Yield?**
- **Definition**: Ratio of passing units to total units tested after packaging.
- **Measurement Point**: After die packaging and burn-in (if applicable).
- **Formula**: FT Yield = (Good Units / Total Units Tested) × 100%.
- **Also Known As**: FT yield, package test yield, class test yield.
**Why Final Test Yield Matters**
- **Last Chance**: Final gate before shipping — no recovery after this.
- **Total Process Health**: Reflects cumulative fab + assembly quality.
- **Cost Per Good Unit**: Directly determines manufacturing cost.
- **Customer Quality**: Lower FT yield often means higher field failures.
- **Capacity Actual vs. Planned**: Determines true factory output.
**Final Test vs. Sort Yield**
**Sort Yield (Wafer Level)**:
- Tests bare die before packaging.
- Catches fab defects.
- Typically 85-99% for mature processes.
**Final Test Yield (Package Level)**:
- Tests packaged units.
- Catches assembly defects + remaining die issues.
- Typically 95-99.9% (higher than sort because bad die already removed).
**Yield Flow Calculation**:
```
1000 wafers × 500 die/wafer = 500,000 die
× 90% Sort Yield = 450,000 good die
× 99% Assembly Yield = 445,500 assembled units
× 98% FT Yield = 436,590 shippable units
Overall Yield = 436,590 / 500,000 = 87.3%
```
**Final Test Components**
**Electrical Tests**:
- **DC Tests**: Continuity, leakage, power supply currents.
- **AC Tests**: Speed, timing, frequency response.
- **Functional Tests**: Logic verification, memory patterns.
- **Parametric Tests**: Voltage/current measurements.
**Stress Tests (Optional)**:
- **Burn-In**: Elevated temperature/voltage to screen infant mortality.
- **HTOL**: High-temperature operating life acceleration.
- **Temperature Cycling**: Thermal stress for package integrity.
**Yield Loss Categories**
- **Assembly Defects**: Wire bond failures, die attach issues, mold voids.
- **Package-Induced**: Stress-related parametric shifts.
- **Test Escapes from Sort**: Die defects missed at wafer probe.
- **ESD Damage**: Handling-induced failures.
- **Tester Correlation**: Units failing due to test equipment issues.
**Yield Improvement Strategies**
- **Sort/FT Correlation**: Analyze which sort failures predict FT failures.
- **Assembly Process Control**: SPC on wire bond, die attach, molding.
- **Test Program Optimization**: Reduce over-testing and false failures.
- **Failure Analysis**: Deep-dive on FT failures for root cause.
- **Supplier Quality**: Monitor outsourced assembly test (OSAT) performance.
**Tools & Equipment**
- **ATE (Automatic Test Equipment)**: Advantest, Teradyne, Cohu.
- **Handlers**: Multisite parallel testing, temperature forcing.
- **Data Analytics**: Test data warehousing, yield management systems.
- **FA Lab**: Decapsulation, X-ray, acoustic microscopy for failure analysis.
Final test yield is **the ultimate measure of manufacturing excellence** — representing the combined quality of design, fab, assembly, and test, it determines how many products actually ship and directly drives revenue, customer satisfaction, and competitive position.