FinFET 2010s Define Fin Geometry and Electrostatic Benefit It Buys
# FinFET (2010s): Step 3 — Define the Fin's Geometry and the Electrostatic Benefit It Buys
## 1. From Concept to Dimensioned Structure
Step 2 established tri-gate wrapping as the fix in principle. Turning that into a manufacturable transistor requires actually dimensioning the fin: a typical early-generation fin runs roughly 8-10 nanometers wide and 40-50 nanometers tall, an aspect ratio near 5:1, standing on a shallow-trench-isolation base that sets how much of the fin's height the gate actually wraps.
## 2. Why the Fin Must Be Both Thin and Tall
Thinness is what buys the electrostatic benefit: a narrower fin shrinks the natural length lambda from Step 2's relation, letting a shorter physical gate length still satisfy the short-channel-immunity condition. Height is what buys back the drive current a thin fin would otherwise sacrifice — because the gate wraps the fin's two sidewalls plus its top, the effective conducting channel width per fin is approximately twice the fin height plus the fin width, so a taller fin delivers more current without consuming more die area in the lateral direction a planar transistor would have needed.
## 3. The Aspect-Ratio Tradeoff This Creates
Pushing fin height up to recover drive current, while holding fin width down to preserve electrostatic control, drives fin aspect ratios that planar process tool sets were never built to etch, isolate, or gate uniformly. Every fabrication challenge the rest of this series' early steps address — patterning pitch, etch profile control, isolation recess precision — traces back to this one tension between a fin thin enough to gate well and tall enough to drive current well.
## 4. What This Step Does and Does Not Cover
This step fixes the fin's governing dimensions and the tradeoff between them; it does not yet address how such a narrow, tall structure is patterned at the pitches production logic requires, which Step 4 takes up directly.