Flicker Noise MOSFET
# Flicker Noise
Every MOSFET has a noise floor that doesn't look like the flat, white thermal noise a resistor produces. Plot a transistor's drain-current noise power against frequency and the low-frequency end climbs steadily as frequency drops, roughly as 1/f — flicker noise, named for that characteristic slope, and it's not a packaging or environmental artifact. It comes from individual charge carriers getting trapped and released at defects sitting right at the silicon-to-gate-oxide interface, directly beneath the channel every drain current has to flow through.
Trap-and-release at the interface is a slow, random process, and slow random processes concentrate their energy at low frequency. The gate oxide's interface with silicon is never perfectly clean at the atomic scale — dangling bonds and defect states sit there, each one capable of capturing a mobile channel carrier for a while and releasing it later. Each individual trap switches between empty and occupied with its own characteristic time constant, and capturing a carrier measurably perturbs the channel's conductance right at that location, since one fewer carrier is available to conduct current at that instant. A single trap with a long time constant produces noise concentrated at low frequency, by the same logic that a slow-blinking light looks steady at a glance but a fast-blinking one looks like noise — and a real device has a whole distribution of traps with time constants spread across many decades, which is exactly what sums into the classic 1/f spectral shape instead of a single bump at one frequency.
The noise power scales inversely with device area, which is the whole reason this noise mechanism matters for analog design decisions. A larger gate area averages over more independent traps, and independent random fluctuations partially cancel rather than adding directly, so flicker-noise power drops roughly as 1/(W·L) — meaning the straightforward way to reduce it is simply to make the transistor physically bigger, trading die area for noise performance. That tradeoff shows up constantly in analog and RF design: the input pair of a precision amplifier, the oscillator core transistors setting an LC-VCO's phase noise, and any low-frequency sensing front-end all get sized specifically to push flicker noise's corner frequency down below the signal band, not just to hit a transconductance target.
pMOS devices typically show lower flicker noise than nMOS for the same sizing, a long-standing asymmetry process technology has had to design around. Hole traps at the oxide interface tend to be less numerous or less electrically active than electron traps in many process technologies, so a pMOS input device often wins a flicker-noise budget for the same area nMOS would need to be made larger to match — a known rule of thumb precision-analog designers at firms building sensor front-ends and data-converter input stages lean on directly when choosing input-pair polarity. High-k gate dielectrics introduced for leakage control at advanced nodes shifted this picture again, since the high-k/interfacial-oxide stack has its own distinct trap density and energy distribution compared to pure SiO2, which is part of why flicker-noise characterization gets re-run for every new gate-stack generation rather than assumed to carry over.
kT/C noise (id 950) sets a hard sampling-time floor no circuit technique can remove. Flicker noise is a different kind of floor — one that rises as frequency falls rather than staying flat, set by the physical quality of the gate-oxide interface itself, and one of the few noise mechanisms in a modern chip that a designer can still buy down directly, just by spending more silicon area.